mirror of https://github.com/OpenIPC/firmware.git
140 lines
3.7 KiB
Diff
140 lines
3.7 KiB
Diff
diff -drupN a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
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--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h 2018-08-06 17:23:04.000000000 +0300
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+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h 2022-06-12 05:28:14.000000000 +0300
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@@ -16,6 +16,8 @@
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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+#define SUNXI_PINCTRL_NAME "sunxi-pinctrl"
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+
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#define PA_BASE 0
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#define PB_BASE 32
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#define PC_BASE 64
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@@ -25,15 +27,37 @@
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#define PG_BASE 192
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#define PH_BASE 224
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#define PI_BASE 256
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+#define PJ_BASE 288
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#define PL_BASE 352
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#define PM_BASE 384
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#define PN_BASE 416
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+#if defined(CONFIG_ARCH_SUN8IW12P1) \
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+ || defined(CONFIG_ARCH_SUN8IW15P1) \
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+ || defined(CONFIG_ARCH_SUN8IW16P1) \
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+ || defined(CONFIG_ARCH_SUN8IW19P1) \
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+ || defined(CONFIG_ARCH_SUN8IW18P1) \
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+ || defined(CONFIG_ARCH_SUN50IW6P1) \
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+ || defined(CONFIG_ARCH_SUN50IW3P1) \
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+ || defined(CONFIG_ARCH_SUN50IW9P1) \
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+ || defined(CONFIG_ARCH_SUN50IW10P1) \
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+ || defined(CONFIG_ARCH_SUN50IW11P1)
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+#define CONFIG_SUNXI_PIO_POWER_MODE
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+#define GPIO_POW_MODE_SEL 0x0340
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+#define GPIO_POW_MODE_VAL 0x0348
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+#define GPIO_POW_MODE_MASK 0xFFF
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+#endif
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+
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+#if defined(CONFIG_ARCH_SUN8IW16P1) \
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+ || defined(CONFIG_ARCH_SUN8IW19P1) \
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+ || defined(CONFIG_ARCH_SUN50IW11P1)
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+#define CONFIG_SUNXI_PIO_POWER_SEL
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+#define GPIO_POW_VOL_SEL 0x0350
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+#endif
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+
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#define SUNXI_PINCTRL_PIN(bank, pin) \
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PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
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-#define SUNXI_PIN_NAME_MAX_LEN 5
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-
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#define BANK_MEM_SIZE 0x24
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#define MUX_REGS_OFFSET 0x0
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#define DATA_REGS_OFFSET 0x10
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@@ -68,8 +92,10 @@
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#define IRQ_STATUS_IRQ_PER_REG 32
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#define IRQ_STATUS_IRQ_BITS 1
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#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
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+#define IRQ_DEBOUNCE_REG 0x218
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#define IRQ_MEM_SIZE 0x20
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+#define IRQ_CFG_SIZE 0x10
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#define IRQ_EDGE_RISING 0x00
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#define IRQ_EDGE_FALLING 0x01
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@@ -78,8 +104,16 @@
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#define IRQ_EDGE_BOTH 0x04
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#define SUN4I_FUNC_INPUT 0
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+#define SUN4I_FUNC_OUTPUT 1
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#define SUN4I_FUNC_IRQ 6
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+#define SYSCFG_PROP_DEFAULT_VAL 0xFFFFFFFF
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+
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+#define SUNXI_PINCTRL_NO_PULL 0
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+#define SUNXI_PINCTRL_PULL_UP 1
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+#define SUNXI_PINCTRL_PULL_DOWN 2
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+
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+
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struct sunxi_desc_function {
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const char *name;
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u8 muxval;
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@@ -96,9 +130,12 @@ struct sunxi_pinctrl_desc {
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const struct sunxi_desc_pin *pins;
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int npins;
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unsigned pin_base;
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+ unsigned int banks;
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+ const unsigned int *bank_base;
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unsigned irq_banks;
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- unsigned irq_bank_base;
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+ const unsigned int *irq_bank_base;
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bool irq_read_needs_mux;
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+ bool disable_strict_mode;
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};
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struct sunxi_pinctrl_function {
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@@ -125,10 +162,21 @@ struct sunxi_pinctrl {
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unsigned ngroups;
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int *irq;
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unsigned *irq_array;
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- spinlock_t lock;
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+ u32 *wake_mask;
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+ u32 *cur_mask;
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+ u32 *wake_debounce;
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+ u32 *cur_debounce;
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+ raw_spinlock_t lock;
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struct pinctrl_dev *pctl_dev;
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+ u32 *regs_backup;
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};
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+#define SUNXI_PIO_BANK_BASE(pin, irq_bank) \
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+ ((pin-PA_BASE)/PINS_PER_BANK - irq_bank)
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+
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+#define SUNXI_R_PIO_BANK_BASE(pin, irq_bank) \
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+ ((pin-PL_BASE)/PINS_PER_BANK - irq_bank)
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+
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#define SUNXI_PIN(_pin, ...) \
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{ \
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.pin = _pin, \
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@@ -284,7 +332,21 @@ static inline u32 sunxi_irq_status_offse
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return irq_num * IRQ_STATUS_IRQ_BITS;
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}
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+static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base)
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+{
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+ return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE;
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+}
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+
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+static inline u32 sunxi_irq_debounce_reg(u16 irq, unsigned bank_base)
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+{
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+ u8 bank = irq / IRQ_PER_BANK;
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+
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+ return sunxi_irq_debounce_reg_from_bank(bank, bank_base);
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+}
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+
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int sunxi_pinctrl_init(struct platform_device *pdev,
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const struct sunxi_pinctrl_desc *desc);
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+extern const struct dev_pm_ops sunxi_pinctrl_pm_ops;
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+
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#endif /* __PINCTRL_SUNXI_H */
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