diff -drupN a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h	2018-08-06 17:23:04.000000000 +0300
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h	2022-06-12 05:28:14.000000000 +0300
@@ -16,6 +16,8 @@
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
 
+#define SUNXI_PINCTRL_NAME "sunxi-pinctrl"
+
 #define PA_BASE	0
 #define PB_BASE	32
 #define PC_BASE	64
@@ -25,15 +27,37 @@
 #define PG_BASE	192
 #define PH_BASE	224
 #define PI_BASE	256
+#define PJ_BASE	288
 #define PL_BASE	352
 #define PM_BASE	384
 #define PN_BASE	416
 
+#if defined(CONFIG_ARCH_SUN8IW12P1) \
+	|| defined(CONFIG_ARCH_SUN8IW15P1) \
+	|| defined(CONFIG_ARCH_SUN8IW16P1) \
+	|| defined(CONFIG_ARCH_SUN8IW19P1) \
+	|| defined(CONFIG_ARCH_SUN8IW18P1) \
+	|| defined(CONFIG_ARCH_SUN50IW6P1) \
+	|| defined(CONFIG_ARCH_SUN50IW3P1) \
+	|| defined(CONFIG_ARCH_SUN50IW9P1) \
+	|| defined(CONFIG_ARCH_SUN50IW10P1) \
+	|| defined(CONFIG_ARCH_SUN50IW11P1)
+#define CONFIG_SUNXI_PIO_POWER_MODE
+#define GPIO_POW_MODE_SEL  0x0340
+#define GPIO_POW_MODE_VAL  0x0348
+#define GPIO_POW_MODE_MASK  0xFFF
+#endif
+
+#if defined(CONFIG_ARCH_SUN8IW16P1) \
+	|| defined(CONFIG_ARCH_SUN8IW19P1) \
+	|| defined(CONFIG_ARCH_SUN50IW11P1)
+#define CONFIG_SUNXI_PIO_POWER_SEL
+#define GPIO_POW_VOL_SEL   0x0350
+#endif
+
 #define SUNXI_PINCTRL_PIN(bank, pin)		\
 	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
 
-#define SUNXI_PIN_NAME_MAX_LEN	5
-
 #define BANK_MEM_SIZE		0x24
 #define MUX_REGS_OFFSET		0x0
 #define DATA_REGS_OFFSET	0x10
@@ -68,8 +92,10 @@
 #define IRQ_STATUS_IRQ_PER_REG		32
 #define IRQ_STATUS_IRQ_BITS		1
 #define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)
+#define IRQ_DEBOUNCE_REG		0x218
 
 #define IRQ_MEM_SIZE		0x20
+#define IRQ_CFG_SIZE		0x10
 
 #define IRQ_EDGE_RISING		0x00
 #define IRQ_EDGE_FALLING	0x01
@@ -78,8 +104,16 @@
 #define IRQ_EDGE_BOTH		0x04
 
 #define SUN4I_FUNC_INPUT	0
+#define SUN4I_FUNC_OUTPUT	1
 #define SUN4I_FUNC_IRQ		6
 
+#define SYSCFG_PROP_DEFAULT_VAL 0xFFFFFFFF
+
+#define SUNXI_PINCTRL_NO_PULL	0
+#define SUNXI_PINCTRL_PULL_UP	1
+#define SUNXI_PINCTRL_PULL_DOWN	2
+
+
 struct sunxi_desc_function {
 	const char	*name;
 	u8		muxval;
@@ -96,9 +130,12 @@ struct sunxi_pinctrl_desc {
 	const struct sunxi_desc_pin	*pins;
 	int				npins;
 	unsigned			pin_base;
+	unsigned int			banks;
+	const unsigned int		*bank_base;
 	unsigned			irq_banks;
-	unsigned			irq_bank_base;
+	const unsigned int		*irq_bank_base;
 	bool				irq_read_needs_mux;
+	bool				disable_strict_mode;
 };
 
 struct sunxi_pinctrl_function {
@@ -125,10 +162,21 @@ struct sunxi_pinctrl {
 	unsigned			ngroups;
 	int				*irq;
 	unsigned			*irq_array;
-	spinlock_t			lock;
+	u32				*wake_mask;
+	u32				*cur_mask;
+	u32				*wake_debounce;
+	u32				*cur_debounce;
+	raw_spinlock_t			lock;
 	struct pinctrl_dev		*pctl_dev;
+	u32				*regs_backup;
 };
 
+#define SUNXI_PIO_BANK_BASE(pin, irq_bank) \
+	((pin-PA_BASE)/PINS_PER_BANK - irq_bank)
+
+#define SUNXI_R_PIO_BANK_BASE(pin, irq_bank) \
+	((pin-PL_BASE)/PINS_PER_BANK - irq_bank)
+
 #define SUNXI_PIN(_pin, ...)					\
 	{							\
 		.pin = _pin,					\
@@ -284,7 +332,21 @@ static inline u32 sunxi_irq_status_offse
 	return irq_num * IRQ_STATUS_IRQ_BITS;
 }
 
+static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base)
+{
+	return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE;
+}
+
+static inline u32 sunxi_irq_debounce_reg(u16 irq, unsigned bank_base)
+{
+	u8 bank = irq / IRQ_PER_BANK;
+
+	return sunxi_irq_debounce_reg_from_bank(bank, bank_base);
+}
+
 int sunxi_pinctrl_init(struct platform_device *pdev,
 		       const struct sunxi_pinctrl_desc *desc);
 
+extern const struct dev_pm_ops sunxi_pinctrl_pm_ops;
+
 #endif /* __PINCTRL_SUNXI_H */