mirror of https://github.com/OpenIPC/firmware.git
109 lines
3.8 KiB
Diff
109 lines
3.8 KiB
Diff
diff -drupN a/drivers/clk/sunxi/clk-sun8iw8.h b/drivers/clk/sunxi/clk-sun8iw8.h
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--- a/drivers/clk/sunxi/clk-sun8iw8.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/clk/sunxi/clk-sun8iw8.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,104 @@
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+/*
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+ * Copyright (C) 2016 Allwinnertech, czy <chenzunyin@allwinnertech.com>
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+ *
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+ * Copyright (C) 2013 Allwinnertech, kevin.z.m <kevin@allwinnertech.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * Adjustable factor-based clock implementation
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+ */
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+#ifndef __MACH_SUNXI_CLK_SUN8IW8_H
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+#define __MACH_SUNXI_CLK_SUN8IW8_H
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clkdev.h>
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+#include <linux/io.h>
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+#include "clk-factors.h"
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+/* register list */
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+#define PLL_CPU 0x0000
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+#define PLL_AUDIO 0x0008
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+#define PLL_VIDEO 0x0010
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+#define PLL_VE 0x0018
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+#define PLL_DDR0 0x0020
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+#define PLL_PERIPH0 0x0028
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+#define PLL_ISP 0x002c
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+#define PLL_PERIPH1 0x0044
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+#define PLL_DDR1 0x004c
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+
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+#define CPU_CFG 0x0050
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+#define AHB1_CFG 0x0054
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+#define APB2_CFG 0x0058
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+#define AHB2_CFG 0x005c
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+#define BUS_GATE0 0x0060
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+#define BUS_GATE1 0x0064
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+#define BUS_GATE2 0x0068
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+#define BUS_GATE3 0x006c
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+#define BUS_GATE4 0x0070
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+
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+#define SD0_CFG 0x0088
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+#define SD1_CFG 0x008c
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+#define SD2_CFG 0x0090
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+#define SS_CFG 0x009c
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+#define SPI0_CFG 0x00A0
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+#define I2S0_CFG 0x00B0
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+#define USB_CFG 0x00CC
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+#define DRAM_CFG 0x00F4
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+#define DDR_CFG 0x00F8
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+#define MBUS_RST 0x00FC
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+#define DRAM_GATE 0x0100
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+
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+#define DE_CFG 0x0104
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+#define TCON_CFG 0x0118
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+#define CSI_MISC 0x0130
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+#define CSI0_CFG 0x0130
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+#define CSI1_CFG 0x0134
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+#define VE_CFG 0x013C
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+#define ADDA_CFG 0x0140
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+#define AVS_CFG 0x0144
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+#define MBUS_CFG 0x015C
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+#define MIPI_CSI 0x016C
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+
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+#define PLL_CPUPAT 0x0280
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+#define PLL_AUDIOPAT 0x0284
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+#define PLL_VIDEOPAT 0x0288
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+#define PLL_VEPAT 0x028C
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+#define PLL_DDR0PAT 0x0290
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+#define PLL_ISPPAT 0x0298
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+#define PLL_PERI1PAT 0x02A4
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+#define PLL_DDR1PAT 0x02AC
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+
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+#define BUS_RST0 0x02C0
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+#define BUS_RST1 0x02C4
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+#define BUS_RST2 0x02C8
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+#define BUS_RST3 0x02D0
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+#define BUS_RST4 0x02D8
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+
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+#define SUNXI_CLK_MAX_REG 0x02D8
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+
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+#define LOSC_OUT_GATE 0x01C20460
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+
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+#define F_N8X7_M0X4(nv,mv) FACTOR_ALL(nv,8,7,0,0,0,mv,0,4,0,0,0,0,0,0,0,0,0)
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+#define F_N8X5_K4X2(nv,kv) FACTOR_ALL(nv,8,5,kv,4,2,0,0,0,0,0,0,0,0,0,0,0,0)
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+#define F_N8X6_M0X2(nv,mv) FACTOR_ALL(nv,8,6,0,0,0,mv,0,2,0,0,0,0,0,0,0,0,0)
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+#define F_N8X5_K4X2_M0X2(nv,kv,mv) FACTOR_ALL(nv,8,5,kv,4,2,mv,0,2,0,0,0,0,0,0,0,0,0)
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+#define F_N8X5_K4X2_M0X2_P16x2(nv, kv, mv, pv) \
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+ FACTOR_ALL(nv, 8, 5, \
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+ kv, 4, 2, \
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+ mv, 0, 2, \
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+ pv, 16, 2, \
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+ 0, 0, 0, 0, 0, 0)
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+
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+#define PLLCPU(n, k, m, p, freq) {F_N8X5_K4X2_M0X2_P16x2(n, k, m, p), freq}
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+#define PLLVIDEO(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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+#define PLLVE(n,m,freq) {F_N8X7_M0X4(n, m), freq}
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+#define PLLDDR0(n, k, m, freq) {F_N8X5_K4X2_M0X2(n,k, m), freq}
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+#define PLLPERIPH(n, k, freq) {F_N8X5_K4X2(n, k), freq}
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+#define PLLGPU(n,m,freq) {F_N8X7_M0X4(n,m),freq}
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+
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+#define PLLDE(n, m, freq) {F_N8X7_M0X4(n, m), freq}
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+#define PLLISP(n,m,freq) {F_N8X7_M0X4(n,m),freq}
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+#define PLLDDR1(n, m, freq) {F_N8X6_M0X2(n, m), freq}
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+
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+#endif
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