diff -drupN a/drivers/clk/sunxi/clk-sun8iw8.h b/drivers/clk/sunxi/clk-sun8iw8.h
--- a/drivers/clk/sunxi/clk-sun8iw8.h	1970-01-01 03:00:00.000000000 +0300
+++ b/drivers/clk/sunxi/clk-sun8iw8.h	2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2016 Allwinnertech, czy <chenzunyin@allwinnertech.com>
+ *
+ * Copyright (C) 2013 Allwinnertech, kevin.z.m <kevin@allwinnertech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Adjustable factor-based clock implementation
+ */
+#ifndef __MACH_SUNXI_CLK_SUN8IW8_H
+#define __MACH_SUNXI_CLK_SUN8IW8_H
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include "clk-factors.h"
+/* register list */
+#define PLL_CPU             0x0000
+#define PLL_AUDIO           0x0008
+#define PLL_VIDEO           0x0010
+#define PLL_VE              0x0018
+#define PLL_DDR0            0x0020
+#define PLL_PERIPH0         0x0028
+#define PLL_ISP             0x002c
+#define PLL_PERIPH1         0x0044
+#define PLL_DDR1            0x004c
+
+#define CPU_CFG             0x0050
+#define AHB1_CFG            0x0054
+#define APB2_CFG            0x0058
+#define AHB2_CFG            0x005c
+#define BUS_GATE0           0x0060
+#define BUS_GATE1           0x0064
+#define BUS_GATE2           0x0068
+#define BUS_GATE3           0x006c
+#define BUS_GATE4           0x0070
+
+#define SD0_CFG             0x0088
+#define SD1_CFG             0x008c
+#define SD2_CFG             0x0090
+#define SS_CFG              0x009c
+#define SPI0_CFG            0x00A0
+#define I2S0_CFG            0x00B0
+#define USB_CFG             0x00CC
+#define DRAM_CFG            0x00F4
+#define DDR_CFG             0x00F8
+#define MBUS_RST            0x00FC
+#define DRAM_GATE           0x0100
+
+#define DE_CFG              0x0104
+#define TCON_CFG            0x0118
+#define CSI_MISC            0x0130
+#define CSI0_CFG            0x0130
+#define CSI1_CFG            0x0134
+#define VE_CFG              0x013C
+#define ADDA_CFG            0x0140
+#define AVS_CFG             0x0144
+#define MBUS_CFG            0x015C
+#define MIPI_CSI            0x016C
+
+#define PLL_CPUPAT          0x0280
+#define PLL_AUDIOPAT        0x0284
+#define PLL_VIDEOPAT        0x0288
+#define PLL_VEPAT           0x028C
+#define PLL_DDR0PAT         0x0290
+#define PLL_ISPPAT          0x0298
+#define PLL_PERI1PAT        0x02A4
+#define PLL_DDR1PAT         0x02AC
+
+#define BUS_RST0            0x02C0
+#define BUS_RST1            0x02C4
+#define BUS_RST2            0x02C8
+#define BUS_RST3            0x02D0
+#define BUS_RST4            0x02D8
+
+#define SUNXI_CLK_MAX_REG   0x02D8
+
+#define LOSC_OUT_GATE       0x01C20460
+
+#define F_N8X7_M0X4(nv,mv) FACTOR_ALL(nv,8,7,0,0,0,mv,0,4,0,0,0,0,0,0,0,0,0)
+#define F_N8X5_K4X2(nv,kv) FACTOR_ALL(nv,8,5,kv,4,2,0,0,0,0,0,0,0,0,0,0,0,0)
+#define F_N8X6_M0X2(nv,mv) FACTOR_ALL(nv,8,6,0,0,0,mv,0,2,0,0,0,0,0,0,0,0,0)
+#define F_N8X5_K4X2_M0X2(nv,kv,mv) FACTOR_ALL(nv,8,5,kv,4,2,mv,0,2,0,0,0,0,0,0,0,0,0)
+#define F_N8X5_K4X2_M0X2_P16x2(nv, kv, mv, pv) \
+			FACTOR_ALL(nv, 8, 5, \
+			kv, 4, 2, \
+			mv, 0, 2, \
+			pv, 16, 2, \
+			0, 0, 0, 0, 0, 0)
+
+#define PLLCPU(n, k, m, p, freq)    {F_N8X5_K4X2_M0X2_P16x2(n, k, m, p), freq}
+#define PLLVIDEO(n, m, freq)        {F_N8X7_M0X4(n, m), freq}
+#define PLLVE(n,m,freq)             {F_N8X7_M0X4(n, m), freq}
+#define PLLDDR0(n, k, m, freq)      {F_N8X5_K4X2_M0X2(n,k, m), freq}
+#define PLLPERIPH(n, k, freq)       {F_N8X5_K4X2(n, k), freq}
+#define PLLGPU(n,m,freq)            {F_N8X7_M0X4(n,m),freq}
+
+#define PLLDE(n, m, freq)           {F_N8X7_M0X4(n, m), freq}
+#define PLLISP(n,m,freq)            {F_N8X7_M0X4(n,m),freq}
+#define PLLDDR1(n, m, freq)         {F_N8X6_M0X2(n, m), freq}
+
+#endif