mirror of https://github.com/OpenIPC/firmware.git
[HI3518EV200] Add DTS profile
Igor Zalatov (from Citadel PC)
parent
743152b68b
commit
e83c4f649f
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@ -0,0 +1,576 @@
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/*
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* Copyright (c) 2013-2014 Linaro Ltd.
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* Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <dt-bindings/clock/hi3518ev20x-clock.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,arm926ej-s";
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reg = <0>;
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};
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};
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vic: interrupt-controller@100d0000 {
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compatible = "arm,pl190-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x100d0000 0x1000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&vic>;
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ranges;
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clock: clock@20030000 {
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compatible = "hisilicon,hi3518ev20x-clock";
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reg = <0x20030000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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};
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sysctrl: system-controller@20050000 {
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compatible = "hisilicon,hi3518ev20x-sysctrl",
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"syscon";
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reg = <0x20050000 0x1000>;
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#clock-cells = <1>;
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&sysctrl>;
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offset = <0x4>;
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mask = <0xdeadbeef>;
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};
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dual_timer0: dual_timer@20000000 {
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compatible = "arm,sp804", "arm,primecell";
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/* timer0 & timer1 */
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interrupts = <3>;
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reg = <0x20000000 0x1000>;
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clocks = <&sysctrl HI3518EV20X_TIME0_0_CLK>,
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<&sysctrl HI3518EV20X_TIME0_1_CLK>,
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<&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "timer0", "timer1", "apb_pclk";
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status = "disabled";
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};
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dual_timer1: dual_timer@20010000 {
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compatible = "arm,sp804", "arm,primecell";
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/* timer2 & timer3 */
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interrupts = <4>;
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reg = <0x20010000 0x1000>;
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clocks = <&sysctrl HI3518EV20X_TIME1_2_CLK>,
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<&sysctrl HI3518EV20X_TIME1_3_CLK>,
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<&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "timer2", "timer3", "apb_pclk";
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status = "disabled";
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};
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uart0: uart@20080000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x20080000 0x1000>;
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interrupts = <5>;
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clocks = <&clock HI3518EV20X_UART0_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart1: uart@20090000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x20090000 0x1000>;
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interrupts = <30>;
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clocks = <&clock HI3518EV20X_UART1_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart2: uart@200a0000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x200a0000 0x1000>;
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interrupts = <25>;
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clocks = <&clock HI3518EV20X_UART2_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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usb_phy: phy {
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compatible = "hisilicon,hisi-usb-phy";
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reg = <0x20030000 0x10000>, <0x20120000 0x10000>,
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<0x20050000 0x10000>;
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#phy-cells = <0>;
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};
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ehci@0x100b0000 {
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compatible = "generic-ehci";
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reg = <0x100b0000 0x10000>;
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interrupts = <15>;
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clocks = <&clock HI3518EV20X_USB2_CTRL_UTMI0_REQ>,
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<&clock HI3518EV20X_USB2_HRST_REQ>;
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clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
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};
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ohci@0x100a0000 {
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compatible = "generic-ohci";
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reg = <0x100a0000 0x10000>;
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interrupts = <16>;
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clocks = <&clock HI3518EV20X_USB2_CTRL_UTMI0_REQ>,
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<&clock HI3518EV20X_USB2_HRST_REQ>;
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clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
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};
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hiudc@0x10080000 {
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compatible = "hiudc";
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reg = <0x10080000 0x10000>;
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interrupts = <10>;
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clocks = <&clock HI3518EV20X_USB2_HRST_REQ>;
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clock-names = "clk";
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};
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i2c_bus0: i2c@200d0000 {
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compatible = "hisilicon,hisi-i2c-hisilicon";
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reg = <0x200d0000 0x100>;
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interrupts = <20>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-frequency = <100000>;
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io-size = <0x1000>;
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id = <0>;
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status = "disabled";
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};
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i2c_bus1: i2c@20240000 {
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compatible = "hisilicon,hisi-i2c-hisilicon";
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reg = <0x20240000 0x100>;
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interrupts = <20>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-frequency = <100000>;
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io-size = <0x1000>;
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id = <1>;
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status = "disabled";
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};
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i2c_bus2: i2c@20250000 {
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compatible = "hisilicon,hisi-i2c-hisilicon";
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reg = <0x20250000 0x100>;
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interrupts = <20>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-frequency = <100000>;
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io-size = <0x1000>;
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id = <2>;
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status = "disabled";
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};
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spi_bus0: spi@200c0000 {
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compatible = "arm,pl022", "arm,primecell";
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arm,primecell-periphid = <0x00800022>;
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reg = <0x200c0000 0x1000>;
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interrupts = <6>;
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clocks = <&clock HI3518EV20X_SPI0_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi_bus1: spi@200e0000 {
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compatible = "arm,pl022", "arm,primecell";
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arm,primecell-periphid = <0x00800022>;
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reg = <0x200e0000 0x1000>, <0x20120004 0x4>;
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interrupts = <7>;
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clocks = <&clock HI3518EV20X_SPI1_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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hisi,spi_cs_sb = <26>;
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hisi,spi_cs_mask_bit = <0x0c000000>;
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};
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fmc: flash-memory-controller@10010000 {
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compatible = "hisilicon,hisi-fmc";
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reg = <0x10010000 0x1000>, <0x58000000 0x10000>;
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reg-names = "control", "memory";
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clocks = <&clock HI3518EV20X_FMC_CLK>;
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#address-cells = <1>;
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#size-cells = <0>;
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hisfc:spi-nor@0 {
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compatible = "hisilicon,fmc-spi-nor";
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assigned-clocks = <&clock HI3518EV20X_FMC_CLK>;
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assigned-clock-rates = <24000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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hisnfc:spi-nand@0 {
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compatible = "hisilicon,fmc-spi-nand";
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assigned-clocks = <&clock HI3518EV20X_FMC_CLK>;
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assigned-clock-rates = <24000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mdio: mdio@10091100 {
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compatible = "hisilicon,hisi-femac-mdio";
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reg = <0x10091100 0x10>;
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clocks = <&clock HI3518EV20X_ETH_CLK>;
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clock-names = "mdio";
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assigned-clocks = <&clock HI3518EV20X_ETH_CLK>;
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assigned-clock-rates = <54000000>;
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resets = <&clock 0xec 3>;
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reset-names = "external-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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hisi_femac: ethernet@10090000 {
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compatible = "hisilicon,hi3518ev20x-femac",
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"hisilicon,hisi-femac-v2";
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reg = <0x10090000 0x1000>,<0x10091300 0x200>;
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interrupts = <12>;
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clocks = <&clock HI3518EV20X_ETH_CLK>;
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resets = <&clock 0xec 0>;
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reset-names = "mac";
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};
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mmc0_emmc: himciv200.MMC@0x10020000{
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compatible = "hisilicon,hi3518ev20x-himci";
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reg = <0x10020000 0x1000>;
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interrupts = <18>;
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clocks = <&clock HI3518EV20X_MMC0_CLK>;
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clock-names = "mmc_clk";
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max-frequency = <99000000>;
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resets = <&clock 0xc4 8>;
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reset-names = "mmc_reset";
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-mmc-hw-reset;
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mmc-hs200-1_8v;
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full-pwr-cycle;
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devid = <0>;
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status = "disabled";
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};
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mmc0_sd: himciv200.SD@0x10020000{
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compatible = "hisilicon,hi3518ev20x-himci";
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reg = <0x10020000 0x1000>;
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interrupts = <18>;
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clocks = <&clock HI3518EV20X_MMC0_CLK>;
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clock-names = "mmc_clk";
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max-frequency = <49500000>;
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resets = <&clock 0xc4 8>;
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reset-names = "mmc_reset";
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bus-width = <4>;
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cap-sd-highspeed;
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devid = <0>;
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status = "disabled";
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};
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mmc1_sd: himciv200.SD@0x10030000{
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compatible = "hisilicon,hi3518ev20x-himci";
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reg = <0x10030000 0x1000>;
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interrupts = <8>;
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clocks = <&clock HI3518EV20X_MMC1_CLK>;
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clock-names = "mmc_clk";
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max-frequency = <49500000>;
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resets = <&clock 0xc4 0>;
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reset-names = "mmc_reset";
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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devid = <1>;
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status = "disabled";
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};
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pmux: pinmux@200f0000 {
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compatible = "pinctrl-single";
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reg = <0x200f0000 0x108>;
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#address-cells = <1>;
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#size-cells = <1>;
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#gpio-range-cells = <3>;
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ranges;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <7>;
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 5 0
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&range 6 38 0 &range 44 1 2
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&range 45 13 0 &range 58 8 1>;
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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};
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pconf: pinconf@200f0800 {
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compatible = "pinconf-single";
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reg = <0x200f0800 0x130>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pinctrl-single,register-width = <32>;
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};
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gpio_chip0: gpio_chip@20140000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x20140000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 28 3>, <&pmux 3 12 1>,
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<&pmux 4 0 4>;
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status = "disabled";
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};
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gpio_chip1: gpio_chip@20150000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x20150000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 31 8>;
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status = "disabled";
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};
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gpio_chip2: gpio_chip@20160000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x20160000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 4 8>;
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status = "disabled";
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};
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gpio_chip3: gpio_chip@20170000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x20170000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 13 8>;
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status = "disabled";
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};
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gpio_chip4: gpio_chip@20180000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x20180000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 21 7>, <&pmux 7 39 1>;
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status = "disabled";
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};
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gpio_chip5: gpio_chip@20190000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x20190000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 40 8>;
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status = "disabled";
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};
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gpio_chip6: gpio_chip@201a0000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x201a0000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 48 8>;
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status = "disabled";
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};
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gpio_chip7: gpio_chip@201b0000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x201b0000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 56 8>;
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status = "disabled";
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};
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gpio_chip8: gpio_chip@201c0000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x201c0000 0x10000>;
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interrupts = <31>;
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clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
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clock-names = "apb_pclk";
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#gpio-cells = <2>;
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gpio-ranges = <&pmux 0 64 2>;
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status = "disabled";
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};
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hidmac: hidma-controller@10060000 {
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compatible = "hisilicon,hisi-dmac";
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reg = <0x10060000 0x1000>;
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interrupts = <14>;
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clocks = <&clock HI3518EV20X_DMAC_CLK>;
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clock-names = "dmac_clk";
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resets = <&clock 0xd8 4>;
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reset-names = "dma-reset";
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#dma-cells = <2>;
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status = "disabled";
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};
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};
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media {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&vic>;
|
||||
ranges;
|
||||
|
||||
sys_config {
|
||||
compatible = "hisilicon,sys_config";
|
||||
};
|
||||
|
||||
sys: sys@20030000 {
|
||||
compatible = "hisilicon,hi35xx_sys";
|
||||
reg = <0x20030000 0x10000>, <0x20050000 0x10000>,
|
||||
<0x20110000 0x10000>, <0x20120000 0x10000>;
|
||||
reg-names = "crg", "sys", "ddr", "misc";
|
||||
};
|
||||
|
||||
audio: audio@20650000 {
|
||||
compatible = "hisilicon,hi35xx_aiao";
|
||||
interrupts = <9>;
|
||||
reg = <0x20650000 0x10000>;
|
||||
reg-names = "aiao";
|
||||
};
|
||||
|
||||
ive: ive@206a0000 {
|
||||
compatible = "hisilicon,hi35xx_ive";
|
||||
interrupts = <21>;
|
||||
reg = <0x206a0000 0x10000>;
|
||||
};
|
||||
|
||||
mipi: mipi@20680000 {
|
||||
compatible = "hisilicon,hi35xx_mipi";
|
||||
interrupts = <28>;
|
||||
reg = <0x20680000 0x10000>;
|
||||
};
|
||||
|
||||
isp: isp@20580000 {
|
||||
compatible = "hisilicon,hi35xx_isp";
|
||||
interrupts = <22>;
|
||||
reg = <0x20580000 0x10000>, <0x205a0000 0x20000>;
|
||||
reg-names = "reg_vicap_base_va", "reg_isp_base_va";
|
||||
};
|
||||
|
||||
viu: viu@20580000 {
|
||||
compatible = "hisilicon,hi35xx_viu";
|
||||
interrupts = <22>;
|
||||
reg = <0x20580000 0x40000>;
|
||||
};
|
||||
|
||||
vou: vou@205c0000 {
|
||||
compatible = "hisilicon,hi35xx_vou";
|
||||
interrupts = <23>;
|
||||
reg = <0x205c0000 0x10000>;
|
||||
};
|
||||
|
||||
vgs: vgs@20630000 {
|
||||
compatible = "hisilicon,hi35xx_vgs";
|
||||
interrupts = <29>;
|
||||
reg = <0x20630000 0x10000>;
|
||||
};
|
||||
|
||||
vpss: vpss@20600000 {
|
||||
compatible = "hisilicon,hi35xx_vpss";
|
||||
interrupts = <17>;
|
||||
reg = <0x20600000 0x10000>;
|
||||
};
|
||||
|
||||
avc: avc@20620000 {
|
||||
compatible = "hisilicon,hi35xx_avc";
|
||||
interrupts = <24>;
|
||||
reg = <0x20620000 0x10000>;
|
||||
};
|
||||
|
||||
jpege: jpege@20660000 {
|
||||
compatible = "hisilicon,hi35xx_jpege";
|
||||
interrupts = <26>;
|
||||
reg = <0x20660000 0x10000>;
|
||||
};
|
||||
|
||||
tde: tde@20610000 {
|
||||
compatible = "hisilicon,hi35xx_tde";
|
||||
interrupts = <27>;
|
||||
reg = <0x20610000 0x10000>;
|
||||
};
|
||||
|
||||
pwm: pwm@20130000 {
|
||||
compatible = "hisilicon,hi3516cv300-pwm";
|
||||
reg = <0x20130000 0x10000>;
|
||||
};
|
||||
|
||||
wtdg: wtdg@20040000 {
|
||||
compatible = "hisilicon,hi_wdg";
|
||||
reg = <0x20040000 0x10000>;
|
||||
reg-names = "wtdg";
|
||||
};
|
||||
|
||||
rtc: rtc@20060000 {
|
||||
compatible = "hisilicon,hi_rtc";
|
||||
interrupts = <2>, <2>;
|
||||
interrupt-names = "rtc", "rtc_temp";
|
||||
reg = <0x20060000 0x10000>;
|
||||
};
|
||||
|
||||
ir: ir@20070000{
|
||||
compatible = "hisilicon,hi_ir";
|
||||
interrupts = <19>;
|
||||
reg = <0x20070000 0x10000>;
|
||||
};
|
||||
|
||||
cipher: cipher@100c0000{
|
||||
compatible = "hisilicon,hi_cipher";
|
||||
interrupts = <13>;
|
||||
reg = <0x100c0000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue