diff --git a/br-ext-chip-hisilicon/board/hi3516cv200/kernel/overlay/arch/arm/boot/dts/hi3518ev20x.dtsi b/br-ext-chip-hisilicon/board/hi3516cv200/kernel/overlay/arch/arm/boot/dts/hi3518ev20x.dtsi new file mode 100644 index 00000000..278ddfbf --- /dev/null +++ b/br-ext-chip-hisilicon/board/hi3516cv200/kernel/overlay/arch/arm/boot/dts/hi3518ev20x.dtsi @@ -0,0 +1,576 @@ +/* + * Copyright (c) 2013-2014 Linaro Ltd. + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <dt-bindings/clock/hi3518ev20x-clock.h> +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0>; + }; + }; + + vic: interrupt-controller@100d0000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x100d0000 0x1000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&vic>; + ranges; + + clock: clock@20030000 { + compatible = "hisilicon,hi3518ev20x-clock"; + reg = <0x20030000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + sysctrl: system-controller@20050000 { + compatible = "hisilicon,hi3518ev20x-sysctrl", + "syscon"; + reg = <0x20050000 0x1000>; + #clock-cells = <1>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; + }; + + dual_timer0: dual_timer@20000000 { + compatible = "arm,sp804", "arm,primecell"; + /* timer0 & timer1 */ + interrupts = <3>; + reg = <0x20000000 0x1000>; + clocks = <&sysctrl HI3518EV20X_TIME0_0_CLK>, + <&sysctrl HI3518EV20X_TIME0_1_CLK>, + <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "timer0", "timer1", "apb_pclk"; + status = "disabled"; + }; + + dual_timer1: dual_timer@20010000 { + compatible = "arm,sp804", "arm,primecell"; + /* timer2 & timer3 */ + interrupts = <4>; + reg = <0x20010000 0x1000>; + clocks = <&sysctrl HI3518EV20X_TIME1_2_CLK>, + <&sysctrl HI3518EV20X_TIME1_3_CLK>, + <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "timer2", "timer3", "apb_pclk"; + status = "disabled"; + }; + + uart0: uart@20080000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20080000 0x1000>; + interrupts = <5>; + clocks = <&clock HI3518EV20X_UART0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart1: uart@20090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x20090000 0x1000>; + interrupts = <30>; + clocks = <&clock HI3518EV20X_UART1_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + uart2: uart@200a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x200a0000 0x1000>; + interrupts = <25>; + clocks = <&clock HI3518EV20X_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + usb_phy: phy { + compatible = "hisilicon,hisi-usb-phy"; + reg = <0x20030000 0x10000>, <0x20120000 0x10000>, + <0x20050000 0x10000>; + #phy-cells = <0>; + }; + + ehci@0x100b0000 { + compatible = "generic-ehci"; + reg = <0x100b0000 0x10000>; + interrupts = <15>; + + clocks = <&clock HI3518EV20X_USB2_CTRL_UTMI0_REQ>, + <&clock HI3518EV20X_USB2_HRST_REQ>; + clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req"; + }; + + ohci@0x100a0000 { + compatible = "generic-ohci"; + reg = <0x100a0000 0x10000>; + interrupts = <16>; + + clocks = <&clock HI3518EV20X_USB2_CTRL_UTMI0_REQ>, + <&clock HI3518EV20X_USB2_HRST_REQ>; + clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req"; + }; + + hiudc@0x10080000 { + compatible = "hiudc"; + reg = <0x10080000 0x10000>; + interrupts = <10>; + + clocks = <&clock HI3518EV20X_USB2_HRST_REQ>; + clock-names = "clk"; + }; + + i2c_bus0: i2c@200d0000 { + compatible = "hisilicon,hisi-i2c-hisilicon"; + reg = <0x200d0000 0x100>; + interrupts = <20>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-frequency = <100000>; + io-size = <0x1000>; + id = <0>; + status = "disabled"; + }; + + i2c_bus1: i2c@20240000 { + compatible = "hisilicon,hisi-i2c-hisilicon"; + reg = <0x20240000 0x100>; + interrupts = <20>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-frequency = <100000>; + io-size = <0x1000>; + id = <1>; + status = "disabled"; + }; + + i2c_bus2: i2c@20250000 { + compatible = "hisilicon,hisi-i2c-hisilicon"; + reg = <0x20250000 0x100>; + interrupts = <20>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-frequency = <100000>; + io-size = <0x1000>; + id = <2>; + status = "disabled"; + }; + + spi_bus0: spi@200c0000 { + compatible = "arm,pl022", "arm,primecell"; + arm,primecell-periphid = <0x00800022>; + reg = <0x200c0000 0x1000>; + interrupts = <6>; + clocks = <&clock HI3518EV20X_SPI0_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi_bus1: spi@200e0000 { + compatible = "arm,pl022", "arm,primecell"; + arm,primecell-periphid = <0x00800022>; + reg = <0x200e0000 0x1000>, <0x20120004 0x4>; + interrupts = <7>; + clocks = <&clock HI3518EV20X_SPI1_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + hisi,spi_cs_sb = <26>; + hisi,spi_cs_mask_bit = <0x0c000000>; + }; + + fmc: flash-memory-controller@10010000 { + compatible = "hisilicon,hisi-fmc"; + reg = <0x10010000 0x1000>, <0x58000000 0x10000>; + reg-names = "control", "memory"; + clocks = <&clock HI3518EV20X_FMC_CLK>; + #address-cells = <1>; + #size-cells = <0>; + + hisfc:spi-nor@0 { + compatible = "hisilicon,fmc-spi-nor"; + assigned-clocks = <&clock HI3518EV20X_FMC_CLK>; + assigned-clock-rates = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + hisnfc:spi-nand@0 { + compatible = "hisilicon,fmc-spi-nand"; + assigned-clocks = <&clock HI3518EV20X_FMC_CLK>; + assigned-clock-rates = <24000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio: mdio@10091100 { + compatible = "hisilicon,hisi-femac-mdio"; + reg = <0x10091100 0x10>; + clocks = <&clock HI3518EV20X_ETH_CLK>; + clock-names = "mdio"; + assigned-clocks = <&clock HI3518EV20X_ETH_CLK>; + assigned-clock-rates = <54000000>; + resets = <&clock 0xec 3>; + reset-names = "external-phy"; + #address-cells = <1>; + #size-cells = <0>; + }; + + hisi_femac: ethernet@10090000 { + compatible = "hisilicon,hi3518ev20x-femac", + "hisilicon,hisi-femac-v2"; + reg = <0x10090000 0x1000>,<0x10091300 0x200>; + interrupts = <12>; + clocks = <&clock HI3518EV20X_ETH_CLK>; + resets = <&clock 0xec 0>; + reset-names = "mac"; + }; + + mmc0_emmc: himciv200.MMC@0x10020000{ + compatible = "hisilicon,hi3518ev20x-himci"; + reg = <0x10020000 0x1000>; + interrupts = <18>; + clocks = <&clock HI3518EV20X_MMC0_CLK>; + clock-names = "mmc_clk"; + max-frequency = <99000000>; + resets = <&clock 0xc4 8>; + reset-names = "mmc_reset"; + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + full-pwr-cycle; + devid = <0>; + status = "disabled"; + }; + + mmc0_sd: himciv200.SD@0x10020000{ + compatible = "hisilicon,hi3518ev20x-himci"; + reg = <0x10020000 0x1000>; + interrupts = <18>; + clocks = <&clock HI3518EV20X_MMC0_CLK>; + clock-names = "mmc_clk"; + max-frequency = <49500000>; + resets = <&clock 0xc4 8>; + reset-names = "mmc_reset"; + bus-width = <4>; + cap-sd-highspeed; + devid = <0>; + status = "disabled"; + }; + + mmc1_sd: himciv200.SD@0x10030000{ + compatible = "hisilicon,hi3518ev20x-himci"; + reg = <0x10030000 0x1000>; + interrupts = <8>; + clocks = <&clock HI3518EV20X_MMC1_CLK>; + clock-names = "mmc_clk"; + max-frequency = <49500000>; + resets = <&clock 0xc4 0>; + reset-names = "mmc_reset"; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + devid = <1>; + status = "disabled"; + }; + + pmux: pinmux@200f0000 { + compatible = "pinctrl-single"; + reg = <0x200f0000 0x108>; + #address-cells = <1>; + #size-cells = <1>; + #gpio-range-cells = <3>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + /* pin base, nr pins & gpio function */ + pinctrl-single,gpio-range = <&range 0 5 0 + &range 6 38 0 &range 44 1 2 + &range 45 13 0 &range 58 8 1>; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + + pconf: pinconf@200f0800 { + compatible = "pinconf-single"; + reg = <0x200f0800 0x130>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + }; + + gpio_chip0: gpio_chip@20140000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20140000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 28 3>, <&pmux 3 12 1>, + <&pmux 4 0 4>; + status = "disabled"; + }; + + gpio_chip1: gpio_chip@20150000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20150000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 31 8>; + status = "disabled"; + }; + + gpio_chip2: gpio_chip@20160000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20160000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 4 8>; + status = "disabled"; + }; + + gpio_chip3: gpio_chip@20170000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20170000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 13 8>; + status = "disabled"; + }; + + gpio_chip4: gpio_chip@20180000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20180000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 21 7>, <&pmux 7 39 1>; + status = "disabled"; + }; + + gpio_chip5: gpio_chip@20190000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x20190000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 40 8>; + status = "disabled"; + }; + + gpio_chip6: gpio_chip@201a0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x201a0000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 48 8>; + status = "disabled"; + }; + + gpio_chip7: gpio_chip@201b0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x201b0000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 56 8>; + status = "disabled"; + }; + + gpio_chip8: gpio_chip@201c0000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x201c0000 0x10000>; + interrupts = <31>; + clocks = <&clock HI3518EV20X_SYSAPB_CLK>; + clock-names = "apb_pclk"; + #gpio-cells = <2>; + gpio-ranges = <&pmux 0 64 2>; + status = "disabled"; + }; + + hidmac: hidma-controller@10060000 { + compatible = "hisilicon,hisi-dmac"; + reg = <0x10060000 0x1000>; + interrupts = <14>; + clocks = <&clock HI3518EV20X_DMAC_CLK>; + clock-names = "dmac_clk"; + resets = <&clock 0xd8 4>; + reset-names = "dma-reset"; + #dma-cells = <2>; + status = "disabled"; + }; + }; + + media { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&vic>; + ranges; + + sys_config { + compatible = "hisilicon,sys_config"; + }; + + sys: sys@20030000 { + compatible = "hisilicon,hi35xx_sys"; + reg = <0x20030000 0x10000>, <0x20050000 0x10000>, + <0x20110000 0x10000>, <0x20120000 0x10000>; + reg-names = "crg", "sys", "ddr", "misc"; + }; + + audio: audio@20650000 { + compatible = "hisilicon,hi35xx_aiao"; + interrupts = <9>; + reg = <0x20650000 0x10000>; + reg-names = "aiao"; + }; + + ive: ive@206a0000 { + compatible = "hisilicon,hi35xx_ive"; + interrupts = <21>; + reg = <0x206a0000 0x10000>; + }; + + mipi: mipi@20680000 { + compatible = "hisilicon,hi35xx_mipi"; + interrupts = <28>; + reg = <0x20680000 0x10000>; + }; + + isp: isp@20580000 { + compatible = "hisilicon,hi35xx_isp"; + interrupts = <22>; + reg = <0x20580000 0x10000>, <0x205a0000 0x20000>; + reg-names = "reg_vicap_base_va", "reg_isp_base_va"; + }; + + viu: viu@20580000 { + compatible = "hisilicon,hi35xx_viu"; + interrupts = <22>; + reg = <0x20580000 0x40000>; + }; + + vou: vou@205c0000 { + compatible = "hisilicon,hi35xx_vou"; + interrupts = <23>; + reg = <0x205c0000 0x10000>; + }; + + vgs: vgs@20630000 { + compatible = "hisilicon,hi35xx_vgs"; + interrupts = <29>; + reg = <0x20630000 0x10000>; + }; + + vpss: vpss@20600000 { + compatible = "hisilicon,hi35xx_vpss"; + interrupts = <17>; + reg = <0x20600000 0x10000>; + }; + + avc: avc@20620000 { + compatible = "hisilicon,hi35xx_avc"; + interrupts = <24>; + reg = <0x20620000 0x10000>; + }; + + jpege: jpege@20660000 { + compatible = "hisilicon,hi35xx_jpege"; + interrupts = <26>; + reg = <0x20660000 0x10000>; + }; + + tde: tde@20610000 { + compatible = "hisilicon,hi35xx_tde"; + interrupts = <27>; + reg = <0x20610000 0x10000>; + }; + + pwm: pwm@20130000 { + compatible = "hisilicon,hi3516cv300-pwm"; + reg = <0x20130000 0x10000>; + }; + + wtdg: wtdg@20040000 { + compatible = "hisilicon,hi_wdg"; + reg = <0x20040000 0x10000>; + reg-names = "wtdg"; + }; + + rtc: rtc@20060000 { + compatible = "hisilicon,hi_rtc"; + interrupts = <2>, <2>; + interrupt-names = "rtc", "rtc_temp"; + reg = <0x20060000 0x10000>; + }; + + ir: ir@20070000{ + compatible = "hisilicon,hi_ir"; + interrupts = <19>; + reg = <0x20070000 0x10000>; + }; + + cipher: cipher@100c0000{ + compatible = "hisilicon,hi_cipher"; + interrupts = <13>; + reg = <0x100c0000 0x10000>; + }; + }; +};