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firmware
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Merge branch 'master' of github:OpenIPC/openipc-2.1

pull/62/head
Igor Zalatov (from Citadel PC) 2021-10-17 18:21:01 +03:00
parent 71d0d6df70 ce4dd29055
commit 983574208a
6 changed files with 191 additions and 44 deletions
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42
br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/13_add_spi_nor_ids.patch 100644
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@ -0,0 +1,42 @@
--- a/drivers/mtd/spi-nor/spi-nor.c 2021-10-13 19:11:27.986167869 +0300
--- b/drivers/mtd/spi-nor/spi-nor.c 2021-10-13 19:12:00.874379209 +0300
@@ -1245,7 +1245,7 @@
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l6436f", INFO(0xc22017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(133) },
+ SPI_NOR_DUAL_READ), CLK_MHZ_2X(133) },
{ "mx25l12835f", INFO(0xc22018, 0, 64 * 1024, 256,
SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
@@ -1299,13 +1299,13 @@
PARAMS(micron_4k), CLK_MHZ_2X(80) },
/* XMC */
- { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
+ { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
+ { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
+ { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
+ { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
/* PMC */
@@ -1464,6 +1464,12 @@
{ "xm_xt25f64b-s", INFO(0x0b4017, 0, 64 * 1024, 128,
SPI_NOR_QUAD_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
+
+ /* FM 3.3v */
+ { "FM25Q64-SOB-T-G",INFO(0xa14017, 0, 64 * 1024, 128,
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
+ { "FM25Q128-SOB-T-G",INFO(0xa14018, 0, 64 * 1024, 256,
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
{ },
};

13
br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/13_add_support_fm25q128a_flash.patch
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@ -1,13 +0,0 @@
--- a/drivers/mtd/spi-nor/spi-nor.c 2021-06-19 13:56:54.523168941 +0000
+++ b/drivers/mtd/spi-nor/spi-nor.c 2021-06-19 14:02:43.947271771 +0000
@@ -1217,6 +1217,10 @@
SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) },
{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(80) },
+
+ { "fm25q128a", INFO(0xa14018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
+
{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(gd), CLK_MHZ_2X(80) },
/* GigaDevice 1.8V */

11
br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/14_mx25l6433f_dual_read.patch
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@ -1,11 +0,0 @@
--- a/drivers/mtd/spi-nor/spi-nor.c 2021-07-09 08:00:01.771026933 +0300
+++ b/drivers/mtd/spi-nor/spi-nor.c 2021-07-09 08:04:33.973630596 +0300
@@ -1249,7 +1249,7 @@
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l6436f", INFO(0xc22017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(133) },
+ SPI_NOR_DUAL_READ), CLK_MHZ_2X(133) },
{ "mx25l12835f", INFO(0xc22018, 0, 64 * 1024, 256,
SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },

20
br-ext-chip-hisilicon/board/hi3516ev200/kernel/patches/15_xmc_dual_read.patch
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@ -1,20 +0,0 @@
--- a/drivers/mtd/spi-nor/spi-nor.c 2021-08-24 08:00:01.771026933 +0300
+++ b/drivers/mtd/spi-nor/spi-nor.c 2021-08-24 08:04:33.973630596 +0300
@@ -1303,13 +1303,13 @@
PARAMS(micron_4k), CLK_MHZ_2X(80) },
/* XMC */
- { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
+ { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
+ { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
+ { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
+ { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
PARAMS(xmc), CLK_MHZ_2X(104) },
/* PMC */

149
general/package/hisilicon-osdrv-hi3516ev300/files/sensor/config/sp2305_i2c_1080p.ini 100644
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@ -0,0 +1,149 @@
[sensor]
Sensor_type =stSnsSp2305Obj ;sensor name
Mode =0 ;WDR_MODE_NONE = 0
;WDR_MODE_BUILT_IN = 1
;WDR_MODE_QUDRA = 2
;WDR_MODE_2To1_LINE = 3
;WDR_MODE_2To1_FRAME = 4
;WDR_MODE_2To1_FRAME_FULL_RATE = 5
;WDR_MODE_3To1_LINE = 6
;WDR_MODE_3To1_FRAME = 7
;WDR_MODE_3To1_FRAME_FULL_RATE = 8
;WDR_MODE_4To1_LINE = 9
;WDR_MODE_4To1_FRAME = 10
;WDR_MODE_4To1_FRAME_FULL_RATE = 11
DllFile = /usr/lib/sensors/libsns_sp2305.so ;sensor lib path
[mode]
input_mode =0 ;INPUT_MODE_MIPI = 0
;INPUT_MODE_SUBLVDS = 1
;INPUT_MODE_LVDS = 2 ...etc
raw_bitness = 10
[mipi]
;----------only for mipi_dev---------
data_type = 1 ;raw data type: 8/10/12/14 bit
;DATA_TYPE_RAW_8BIT = 0,
;DATA_TYPE_RAW_10BIT,
;DATA_TYPE_RAW_12BIT,
;DATA_TYPE_RAW_14BIT,
;DATA_TYPE_RAW_16BIT,
;DATA_TYPE_YUV420_8BIT_NORMAL,
;DATA_TYPE_YUV420_8BIT_LEGACY,
;DATA_TYPE_YUV422_8BIT,
lane_id = 0|1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable
[isp_image]
Isp_x =0
Isp_y =0
Isp_W =1920
Isp_H =1080
Isp_FrameRate=25
Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3
[vi_dev]
Input_mod = 6
; VI_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
; VI_MODE_BT656_PACKED_YUV, /* ITU-R BT.656 packed YUV4:2:2 */
; VI_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
; VI_MODE_DIGITAL_CAMERA, /* digatal camera mode */
; VI_MODE_BT1120_STANDARD, /* BT.1120 progressive mode */
; VI_MODE_BT1120_INTERLEAVED, /* BT.1120 interstage mode */
; VI_MODE_MIPI, /* MIPI RAW mode */
; VI_MODE_MIPI_YUV420_NORMAL, /* MIPI YUV420 normal mode */
; VI_MODE_MIPI_YUV420_LEGACY, /* MIPI YUV420 legacy mode */
; VI_MODE_MIPI_YUV422, /* MIPI YUV422 mode */
; VI_MODE_LVDS, /* LVDS mode */
; VI_MODE_HISPI, /* HiSPi mode */
; VI_MODE_SLVS, /* SLVS mode */
Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
;VI_WORK_MODE_2Multiplex,
;VI_WORK_MODE_4Multiplex
Combine_mode =0 ;Y/C composite or separation mode
;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
;VI_COMBINE_SEPARATE, /*Separate mode */
Comp_mode =0 ;Component mode (single-component or dual-component)
;VI_COMP_MODE_SINGLE = 0, /*single component mode */
;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
Mask_num =2 ;Component mask
Mask_0 =0xFFF00000
Mask_1 =0x0
Scan_mode = 1;VI_SCAN_INTERLACED = 0
;VI_SCAN_PROGRESSIVE,
Data_seq =2 ;data sequence (ONLY for YUV format)
;----2th component U/V sequence in bt1120
; VI_INPUT_DATA_VUVU = 0,
; VI_INPUT_DATA_UVUV,
;----input sequence for yuv
; VI_INPUT_DATA_UYVY = 0,
; VI_INPUT_DATA_VYUY,
; VI_INPUT_DATA_YUYV,
; VI_INPUT_DATA_YVYU
Vsync =1 ; vertical synchronization signal
;VI_VSYNC_FIELD = 0,
;VI_VSYNC_PULSE,
VsyncNeg=1 ;Polarity of the vertical synchronization signal
;VI_VSYNC_NEG_HIGH = 0,
;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
Hsync =0 ;Attribute of the horizontal synchronization signal
;VI_HSYNC_VALID_SINGNAL = 0,
;VI_HSYNC_PULSE,
HsyncNeg =0 ;Polarity of the horizontal synchronization signal
;VI_HSYNC_NEG_HIGH = 0,
;VI_HSYNC_NEG_LOW
VsyncValid =1 ;Attribute of the valid vertical synchronization signal
;VI_VSYNC_NORM_PULSE = 0,
;VI_VSYNC_VALID_SINGAL,
VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
;VI_VSYNC_VALID_NEG_HIGH = 0,
;VI_VSYNC_VALID_NEG_LOW
Timingblank_HsyncHfb =0 ;Horizontal front blanking width
Timingblank_HsyncAct =1920 ;Horizontal effetive width
Timingblank_HsyncHbb =0 ;Horizontal back blanking width
Timingblank_VsyncVfb =0 ;Vertical front blanking height
Timingblank_VsyncVact =1080 ;Vertical effetive width
Timingblank_VsyncVbb=0 ;Vertical back blanking height
Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
;----- only for bt656 ----------
FixCode =0 ;BT656_FIXCODE_1 = 0,
;BT656_FIXCODE_0
FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0
;BT656_FIELD_POLAR_NSTD
DataPath =1 ;ISP enable or bypass
;VI_PATH_BYPASS = 0,/* ISP bypass */
;VI_PATH_ISP = 1,/* ISP enable */
;VI_PATH_RAW = 2,/* Capture raw data, for debug */
InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
DevRect_x=200 ;
DevRect_y=20 ;
DevRect_w=1920 ;
DevRect_h=1080 ;
[vi_chn]
CapRect_X =0
CapRect_Y =0
CapRect_Width=1920
CapRect_Height=1080
DestSize_Width=1920
DestSize_Height=1080
CapSel =2 ;Frame/field select. ONLY used in interlaced mode
;VI_CAPSEL_TOP = 0, /* top field */
;VI_CAPSEL_BOTTOM, /* bottom field */
;VI_CAPSEL_BOTH, /* top and bottom field */
PixFormat =26;PIXEL_FORMAT_YVU_SEMIPLANAR_420 = 26 ...etc
CompressMode =0 ;COMPRESS_MODE_NONE = 0
;COMPRESS_MODE_SEG =1 ...etc
SrcFrameRate=-1 ;Source frame rate. -1: not controll
FrameRate =-1 ;Target frame rate. -1: not controll

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general/package/hisilicon-osdrv-hi3516ev300/files/sensor/libsns_sp2305.so 100644
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