Fix OV4689 for Hi3516Dv100

Add OS05A (needs additional init)

general/package/hisilicon-osdrv-hi3516av100/files/script/load_hisilicon

@@ -239,6 +239,12 @@ insert_sns() {
 
                 devmem 0x2003002c 32 0xB0007 # sensor unreset, clk 27MHz, VI 250MHz
                 ;;
+        os05a)
+                devmem 0x200f0050 32 0x2 # i2c0_scl
+                devmem 0x200f0054 32 0x2 # i2c0_sda
+                devmem 0x2003002c 32 0xE0003 # sensor unreset, clk 24MHz, VI 297MHz
+                devmem 0x20030104 32 0x0 # Sensor 24M
+                ;;
         bt1120) ;;
 
         \

general/package/hisilicon-osdrv-hi3516av100/files/sensor/config/os05a_i2c_5M.ini

@@ -0,0 +1,80 @@
+[sensor]
+Sensor_type=os05a
+Mode=WDR_MODE_NONE
+DllFile=libsns_os05a10.so
+
+[mode]
+input_mode=INPUT_MODE_MIPI
+dev_attr=0
+
+[mipi]
+data_type=2
+lane_id=0|1|2|3|-1|-1|-1|-1|
+
+[isp_image]
+Isp_FrameRate=30
+Isp_Bayer=BAYER_BGGR
+
+[vi_dev]
+Input_mod=5
+Work_mod =0     ;VI_WORK_MODE_1Multiplex = 0
+                ;VI_WORK_MODE_2Multiplex,
+                ;VI_WORK_MODE_4Multiplex
+Combine_mode =0 ;Y/C composite or separation mode
+                ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
+                ;VI_COMBINE_SEPARATE,     /*Separate mode */
+Comp_mode    =0 ;Component mode (single-component or dual-component)
+                ;VI_COMP_MODE_SINGLE = 0, /*single component mode */
+                ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
+Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge)
+                ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
+                ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
+Mask_num     =2 ;Component mask
+Mask_0       =0xFFF00000
+Mask_1       =0x0
+Scan_mode    = 1;VI_SCAN_INTERLACED = 0
+                ;VI_SCAN_PROGRESSIVE,
+Data_seq     =3 ;data sequence (ONLY for YUV format)
+                ;----2th component U/V sequence in bt1120
+                ;    VI_INPUT_DATA_VUVU = 0,
+                ;    VI_INPUT_DATA_UVUV,
+                ;----input sequence for yuv
+                ;    VI_INPUT_DATA_UYVY = 0,
+                ;    VI_INPUT_DATA_VYUY,
+                ;    VI_INPUT_DATA_YUYV,
+                ;    VI_INPUT_DATA_YVYU
+
+Vsync   =1      ; vertical synchronization signal
+                ;VI_VSYNC_FIELD = 0,
+                ;VI_VSYNC_PULSE,
+VsyncNeg=1      ;Polarity of the vertical synchronization signal
+                ;VI_VSYNC_NEG_HIGH = 0,
+                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
+Hsync  =0       ;Attribute of the horizontal synchronization signal
+                ;VI_HSYNC_VALID_SINGNAL = 0,
+                ;VI_HSYNC_PULSE,
+HsyncNeg =0     ;Polarity of the horizontal synchronization signal
+                ;VI_HSYNC_NEG_HIGH = 0,
+                ;VI_HSYNC_NEG_LOW
+VsyncValid =1   ;Attribute of the valid vertical synchronization signal
+                ;VI_VSYNC_NORM_PULSE = 0,
+                ;VI_VSYNC_VALID_SINGAL,
+VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
+                ;VI_VSYNC_VALID_NEG_HIGH = 0,
+                ;VI_VSYNC_VALID_NEG_LOW
+Timingblank_HsyncHfb =0     ;Horizontal front blanking width
+Timingblank_HsyncAct =1280  ;Horizontal effetive width
+Timingblank_HsyncHbb =0     ;Horizontal back blanking width
+Timingblank_VsyncVfb =0     ;Vertical front blanking height
+Timingblank_VsyncVact =720  ;Vertical effetive width
+Timingblank_VsyncVbb=0      ;Vertical back blanking height
+Timingblank_VsyncVbfb =0    ;Even-field vertical front blanking height(interlace, invalid progressive)
+Timingblank_VsyncVbact=0    ;Even-field vertical effetive width(interlace, invalid progressive)
+Timingblank_VsyncVbbb =0    ;Even-field vertical back blanking height(interlace, invalid progressive)
+DataPath=1
+InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
+DataRev      =FALSE ;Data reverse. FALSE = 0; TRUE = 1
+DevRect_x=0
+DevRect_y=0
+DevRect_w=2592
+DevRect_h=1944

general/package/hisilicon-osdrv-hi3516av100/files/sensor/config/ov4689_i2c_4M.ini

@@ -1,40 +1,22 @@
 [sensor]
-Sensor_type   =ov4689                   ;sensor name
+Sensor_type=ov4689
-Mode          =0                        ;WDR_MODE_NONE = 0
+Mode=WDR_MODE_NONE
-                                        ;WDR_MODE_BUILT_IN = 1
+DllFile=libsns_ov4689.so
-                                        ;WDR_MODE_2To1_LINE = 2
-                                        ;WDR_MODE_2To1_FRAME = 3
-                                        ;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
-DllFile   =libsns_ov4689.so             ;sensor lib path
 
+[mode]
+input_mode=INPUT_MODE_MIPI
+dev_attr=0
 
-[mode]                               
+[mipi]
-input_mode =0                           ;INPUT_MODE_MIPI = 0
+data_type=RAW_DATA_12BIT
-                                        ;INPUT_MODE_SUBLVDS = 1
+lane_id=0|1|2|3|-1|-1|-1|-1|
-                                        ;INPUT_MODE_LVDS = 2 ...etc
-
-dev_attr = 0                         	;mipi_dev_attr_t = 0
-                                        ;lvds_dev_attr_t = 1
-                                        ;NULL =2
-
-[mipi]    
-;----------only for mipi_dev---------               
-data_type =2                        	;raw data type: 8/10/12/14 bit
-                                        ;RAW_DATA_8BIT = 0
-                                        ;RAW_DATA_10BIT = 1
-                                        ;RAW_DATA_12BIT = 2 
-                                        ;RAW_DATA_14BIT = 3 
-lane_id = 1|0|2|3|-1|-1|-1|-1|          ;lane_id: -1 - disable
 
 [isp_image]
 Isp_FrameRate=25
-Isp_Bayer  =3   ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3 
+Isp_Bayer=BAYER_BGGR
-
 
 [vi_dev]
-Input_mod =5    ;VI_INPUT_MODE_BT656 = 0
+Input_mod=VI_MODE_MIPI
-                ;VI_INPUT_MODE_BT601,
-                ;VI_INPUT_MODE_DIGITAL_CAMERA
 Work_mod =0     ;VI_WORK_MODE_1Multiplex = 0
                 ;VI_WORK_MODE_2Multiplex,
                 ;VI_WORK_MODE_4Multiplex
@@ -48,7 +30,7 @@ Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge)
                 ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
                 ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
 Mask_num     =2 ;Component mask
-Mask_0       =0xfff00000
+Mask_0       =0xFFF00000
 Mask_1       =0x0
 Scan_mode    = 1;VI_SCAN_INTERLACED = 0
                 ;VI_SCAN_PROGRESSIVE,
@@ -61,25 +43,25 @@ Data_seq     =2 ;data sequence (ONLY for YUV format)
                 ;    VI_INPUT_DATA_VYUY,
                 ;    VI_INPUT_DATA_YUYV,
                 ;    VI_INPUT_DATA_YVYU
-                
+
 Vsync   =1      ; vertical synchronization signal
-                ;VI_VSYNC_FIELD = 0, 
+                ;VI_VSYNC_FIELD = 0,
                 ;VI_VSYNC_PULSE,
 VsyncNeg=0      ;Polarity of the vertical synchronization signal
-                ;VI_VSYNC_NEG_HIGH = 0, 
+                ;VI_VSYNC_NEG_HIGH = 0,
-                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E 
+                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
 Hsync  =0       ;Attribute of the horizontal synchronization signal
                 ;VI_HSYNC_VALID_SINGNAL = 0,
                 ;VI_HSYNC_PULSE,
 HsyncNeg =0     ;Polarity of the horizontal synchronization signal
-                ;VI_HSYNC_NEG_HIGH = 0, 
+                ;VI_HSYNC_NEG_HIGH = 0,
                 ;VI_HSYNC_NEG_LOW
 VsyncValid =1   ;Attribute of the valid vertical synchronization signal
                 ;VI_VSYNC_NORM_PULSE = 0,
-                ;VI_VSYNC_VALID_SINGAL, 
+                ;VI_VSYNC_VALID_SINGAL,
 VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
                 ;VI_VSYNC_VALID_NEG_HIGH = 0,
-                ;VI_VSYNC_VALID_NEG_LOW 
+                ;VI_VSYNC_VALID_NEG_LOW
 Timingblank_HsyncHfb =0     ;Horizontal front blanking width
 Timingblank_HsyncAct =2592  ;Horizontal effetive width
 Timingblank_HsyncHbb =0     ;Horizontal back blanking width
@@ -89,20 +71,10 @@ Timingblank_VsyncVbb=0      ;Vertical back blanking height
 Timingblank_VsyncVbfb =0    ;Even-field vertical front blanking height(interlace, invalid progressive)
 Timingblank_VsyncVbact=0    ;Even-field vertical effetive width(interlace, invalid progressive)
 Timingblank_VsyncVbbb =0    ;Even-field vertical back blanking height(interlace, invalid progressive)
-
+DataPath=1
-;----- only for bt656 ----------
-FixCode   =0    ;BT656_FIXCODE_1 = 0,
-                ;BT656_FIXCODE_0 
-FieldPolar=0    ;BT656_FIELD_POLAR_STD = 0
-                ;BT656_FIELD_POLAR_NSTD
-DataPath  =1    ;ISP enable or bypass
-                ;VI_PATH_BYPASS    = 0,/* ISP bypass */
-                ;VI_PATH_ISP       = 1,/* ISP enable */
-                ;VI_PATH_RAW       = 2,/* Capture raw data, for debug */
 InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
 DataRev      =FALSE ;Data reverse. FALSE = 0; TRUE = 1
-DevRect_x=0     ;
+DevRect_x=0
-DevRect_y=0     ;
+DevRect_y=0
-DevRect_w=2592  ;
+DevRect_w=2592
-DevRect_h=1520  ;
+DevRect_h=1520
-