mirror of https://github.com/OpenIPC/firmware.git
Added support for SOI F23 DC sensor (#1110)
Co-authored-by: Yuuki Hogo <yuuki@yandex.ru>pull/1116/head
parent
cd0b448044
commit
806b273a80
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@ -161,7 +161,7 @@ insert_isp_piris() {
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}
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insert_ko() {
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if [ "$SENSOR" == "bt656" ]; then
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if [ "$SENSOR" == "bt656" ] || [ "$SENSOR" == "jxf23_dc" ]; then
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YUV_TYPE0=1
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fi
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modprobe open_sys_config chip=$CHIP_TYPE sensors=$SENSOR g_cmos_yuv_flag=$YUV_TYPE0 board=$BOARD
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@ -0,0 +1,98 @@
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[sensor]
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Sensor_type=stSnsSoiSensorObj
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Mode=WDR_MODE_NONE
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DllFile=libsns_f23_dc.so
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[mode]
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input_mode=INPUT_MODE_CMOS
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raw_bitness=10
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[mipi]
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lane_id = 0|2|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable
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[isp_image]
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Isp_FrameRate=25
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Isp_Bayer=BAYER_BGGR
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[vi_dev]
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Input_mod=VI_MODE_DIGITAL_CAMERA
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Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
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;VI_WORK_MODE_2Multiplex,
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;VI_WORK_MODE_4Multiplex
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Combine_mode =0 ;Y/C composite or separation mode
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;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
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;VI_COMBINE_SEPARATE, /*Separate mode */
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Comp_mode =0 ;Component mode (single-component or dual-component)
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;VI_COMP_MODE_SINGLE = 0, /*single component mode */
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;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
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Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
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;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
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;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
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Mask_num =2 ;Component mask
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Mask_0 =0xFF300000
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Mask_1 =0x0
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Scan_mode = 1;VI_SCAN_INTERLACED = 0
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;VI_SCAN_PROGRESSIVE,
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Data_seq = VI_DATA_SEQ_YUYV ;data sequence (ONLY for YUV format)
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;----2th component U/V sequence in bt1120
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; VI_INPUT_DATA_VUVU = 0,
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; VI_INPUT_DATA_UVUV,
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;----input sequence for yuv
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; VI_INPUT_DATA_UYVY = 0,
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; VI_INPUT_DATA_VYUY,
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; VI_INPUT_DATA_YUYV,
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; VI_INPUT_DATA_YVYU
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Vsync =0 ; vertical synchronization signal
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;VI_VSYNC_FIELD = 0,
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;VI_VSYNC_PULSE,
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VsyncNeg=0 ;Polarity of the vertical synchronization signal
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;VI_VSYNC_NEG_HIGH = 0,
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;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
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Hsync =0 ;Attribute of the horizontal synchronization signal
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;VI_HSYNC_VALID_SINGNAL = 0,
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;VI_HSYNC_PULSE,
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HsyncNeg =0 ;Polarity of the horizontal synchronization signal
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;VI_HSYNC_NEG_HIGH = 0,
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;VI_HSYNC_NEG_LOW
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VsyncValid =1 ;Attribute of the valid vertical synchronization signal
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;VI_VSYNC_NORM_PULSE = 0,
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;VI_VSYNC_VALID_SINGAL,
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VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
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;VI_VSYNC_VALID_NEG_HIGH = 0,
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;VI_VSYNC_VALID_NEG_LOW
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Timingblank_HsyncHfb =0 ;Horizontal front blanking width
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Timingblank_HsyncAct =1920 ;Horizontal effetive width
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Timingblank_HsyncHbb =0 ;Horizontal back blanking width
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Timingblank_VsyncVfb =0 ;Vertical front blanking height
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Timingblank_VsyncVact =1080 ;Vertical effetive width
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Timingblank_VsyncVbb=0 ;Vertical back blanking height
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Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
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Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
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Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
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InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
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DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
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DevRect_x=200
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DevRect_y=20
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DevRect_w=1920
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DevRect_h=1080
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;[vi_chn]
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;CapRect_X =0
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;CapRect_Y =0
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;CapRect_Width=1920
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;CapRect_Height=1080
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;DestSize_Width=1920
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;DestSize_Height=1080
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;CapSel =2 ;Frame/field select. ONLY used in interlaced mode
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;VI_CAPSEL_TOP = 0, /* top field */
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;VI_CAPSEL_BOTTOM, /* bottom field */
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;VI_CAPSEL_BOTH, /* top and bottom field */
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;PixFormat =26;PIXEL_FORMAT_YVU_SEMIPLANAR_420 = 26 ...etc
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;CompressMode =0 ;COMPRESS_MODE_NONE = 0
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;COMPRESS_MODE_SEG =1 ...etc
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SrcFrameRate=30 ;Source frame rate. -1: not controll
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FrameRate =30 ;Target frame rate. -1: not controll
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