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[GK7205V200] Rollback SPI flash patches

pull/257/head
Igor Zalatov (from Citadel PC) 2022-07-01 18:55:52 +03:00
parent 23fe48e931
commit 79bd2def2a
4 changed files with 366 additions and 2821 deletions
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2821
br-ext-chip-goke/board/gk7205v200/kernel/overlay/drivers/mtd/spi-nor/spi-nor.c
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File diff suppressed because it is too large Load Diff

39
br-ext-chip-goke/board/gk7205v200/kernel/patches/13_add_bp_for_xtx_fm_spi_nor.patch 100644
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@ -0,0 +1,39 @@
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1107,7 +1107,7 @@
.reads[SNOR_MIDX_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4),
.reads[SNOR_MIDX_1_4_4] = SNOR_OP_READ(0, 24, SPINOR_OP_READ_1_4_4),
- .wr_modes = SNOR_WR_MODES,
+ .wr_modes = SNOR_MODE_1_1_1,
.page_programs[SNOR_MIDX_1_1_1] = SPINOR_OP_PP,
.page_programs[SNOR_MIDX_1_1_4] = SPINOR_OP_PP_1_1_4,
@@ -2251,6 +2251,8 @@
/* read the BP bit in RDSR to check whether nor is lock or not */
switch (JEDEC_MFR(info)) {
case SNOR_MFR_GD:
+ case SNOR_MFR_FM:
+ case SNOR_MFR_XTX:
case SNOR_MFR_ESMT:
case SNOR_MFR_EON:
case SNOR_MFR_SPANSION:
@@ -2607,6 +2609,8 @@
/* NOR protection support for STmicro/Micron chips and similar */
if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
JEDEC_MFR(info) == SNOR_MFR_WINBOND ||
+ JEDEC_MFR(info) == SNOR_MFR_XTX ||
+ JEDEC_MFR(info) == SNOR_MFR_FM ||
info->flags & SPI_NOR_HAS_LOCK) {
nor->flash_lock = stm_lock;
nor->flash_unlock = stm_unlock;
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -31,6 +31,7 @@
#define SNOR_MFR_GD 0xc8
#define SNOR_MFR_XTX 0x0b
#define SNOR_MFR_PUYA 0x85
+#define SNOR_MFR_FM 0xa1
#define SNOR_MFR_ISSI 0x9d
/* Flash set the RESET# from */

15
br-ext-chip-goke/board/gk7205v200/kernel/patches/15-add-sk-spi-flash.patch 100644
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@ -0,0 +1,15 @@
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1595,6 +1595,12 @@
{ "ZB25VQ64A",INFO(0x5e4017, 0, 64 * 1024, 128,
SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(104) },
+
+ /* SiliconKaiser 3.3v */
+ { "sk25p128", INFO(0x256018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
+
+ { "sk25p64", INFO(0x256017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
+
{ },
};

312
br-ext-chip-goke/board/gk7205v200/kernel/patches/16-spi-nor-disable-quad-and-downclock.patch 100644
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@ -0,0 +1,312 @@
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1266,26 +1266,26 @@
{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64,
- SPI_NOR_QUAD_READ), PARAMS(eon), CLK_MHZ_2X(104) },
+ SPI_NOR_DUAL_READ), PARAMS(eon), CLK_MHZ_2X(80) },
{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(eon), CLK_MHZ_2X(104) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(eon), CLK_MHZ_2X(80) },
{ "en25qh32b-104hip2b", INFO(0x1c7016, 0, 64 * 1024, 64,
- SPI_NOR_QUAD_READ), PARAMS(eon), CLK_MHZ_2X(133) },
+ SPI_NOR_DUAL_READ), PARAMS(eon), CLK_MHZ_2X(80) },
{ "en25qh64a", INFO(0x1c7017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(eon), CLK_MHZ_2X(104) },
+ SPI_NOR_DUAL_READ), PARAMS(eon), CLK_MHZ_2X(80) },
{ "en25q128", INFO(0x1c3018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(eon), CLK_MHZ_2X(104) },
+ SPI_NOR_DUAL_READ), PARAMS(eon), CLK_MHZ_2X(80) },
{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
{ "en25qh128a", INFO(0x1c7018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(eon), CLK_MHZ_2X(104) },
+ SPI_NOR_DUAL_READ), PARAMS(eon), CLK_MHZ_2X(80) },
{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
/* ESMT */
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(esmt), CLK_MHZ_2X(84) },
+ SPI_NOR_DUAL_READ), PARAMS(esmt), CLK_MHZ_2X(84) },
/* Everspin */
{ "mr25h256", CAT25_INFO(32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE
@@ -1298,22 +1298,22 @@
/* GigaDevice 3.3V */
{ "gd25q16c", INFO(0xc84015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(120) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
{ "gd25q128/gd25q127", INFO(0xc84018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(80) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(gd), CLK_MHZ_2X(80) },
/* GigaDevice 1.8V */
{ "gd25lq16c", INFO(0xc86015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(104) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
{ "gd25lq64", INFO(0xc86017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(133) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
{ "gd25lq128", INFO(0xc86018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(gd), CLK_MHZ_2X(133) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(gd), CLK_MHZ_2X(80) },
/* Intel/Numonyx -- xxxs33b */
{ "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
@@ -1324,7 +1324,7 @@
{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
{ "IS25WP512M-RMLA3", INFO(0x9d701a, 0, 64 * 1024, 1024,
- SPI_NOR_QUAD_READ), PARAMS(issi), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(issi), CLK_MHZ_2X(80) },
/* Macronix/MXIC 3.3V */
{ "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
@@ -1336,9 +1336,9 @@
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l6436f", INFO(0xc22017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(133) },
+ SPI_NOR_DUAL_READ), CLK_MHZ_2X(80) },
{ "mx25l12835f", INFO(0xc22018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
+ SPI_NOR_DUAL_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
{ "mx25l25635f", INFO(0xc22019, 0, 64 * 1024, 512,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(84) },
@@ -1346,61 +1346,61 @@
| SPI_NOR_4B_OPCODES) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235l/mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(133)},
+ SPI_NOR_DUAL_READ), PARAMS(mxic), CLK_MHZ_2X(80)},
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)},
{ "mx25v1635f", INFO(0xc22315, 0, 64 * 1024, 32 ,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(mxic), CLK_MHZ_2X(80) },
/* Macronix/MXIC Wide Voltage Range 1.65~3.6V */
{ "mx25r6435f", INFO(0xc22817, 0, 64 * 1024, 128,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ), CLK_MHZ_2X(80) },
/* Macronix/MXIC 1.8V */
{ "mx25u1633f", INFO(0xc22535, 0, 64 * 1024, 32,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(mxic), CLK_MHZ_2X(80) },
{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
{ "mx25u12835f/mx25u12832f", INFO(0xc22538, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
+ SPI_NOR_DUAL_READ), PARAMS(mxic), CLK_MHZ_2X(84) },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(84) },
{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(166) },
{ "mx66u1g45gm", INFO(0xc2253b, 0, 64 * 1024, 2048,
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(133) },
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(mxic), CLK_MHZ_2X(80) },
/* Micron 3.3V */
- { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ),
+ { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_DUAL_READ),
PARAMS(micron), CLK_MHZ_2X(84) },
- { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
+ { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
PARAMS(micron_4k), CLK_MHZ_2X(108) },
- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
+ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
PARAMS(micron), CLK_MHZ_2X(108) },
- { "mt25ql256a", INFO(0x20ba19, 0x1044, 64 * 1024, 512, SPI_NOR_QUAD_READ),
+ { "mt25ql256a", INFO(0x20ba19, 0x1044, 64 * 1024, 512, SPI_NOR_DUAL_READ),
PARAMS(micron), CLK_MHZ_2X(108) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR),
PARAMS(micron_4k) },
- { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR | SPI_NOR_QUAD_READ),
+ { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR | SPI_NOR_DUAL_READ),
PARAMS(micron_4k), CLK_MHZ_2X(80) },
/* Micron 1.8V */
- { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ),
+ { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_DUAL_READ),
PARAMS(micron), CLK_MHZ_2X(108) },
- { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
+ { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
PARAMS(micron), CLK_MHZ_2X(108) },
- { "mt25qu128a/n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
+ { "mt25qu128a/n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
PARAMS(micron), CLK_MHZ_2X(108) },
{ "mt25qu256a", INFO(0x20bb19, 0, 64 * 1024, 512,
- SPI_NOR_4B_OPCODES | SPI_NOR_QUAD_READ), PARAMS(micron), CLK_MHZ_2X(108) },
- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, USE_FSR | SPI_NOR_QUAD_READ),
+ SPI_NOR_4B_OPCODES | SPI_NOR_DUAL_READ), PARAMS(micron), CLK_MHZ_2X(108) },
+ { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, USE_FSR | SPI_NOR_DUAL_READ),
PARAMS(micron_4k), CLK_MHZ_2X(80) },
/* XMC */
- { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
- PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ),
- PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
- PARAMS(xmc), CLK_MHZ_2X(104) },
- { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ),
- PARAMS(xmc), CLK_MHZ_2X(104) },
+ { "xm25qh64a", INFO(0x207017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
+ PARAMS(xmc), CLK_MHZ_2X(80) },
+ { "xm25qh64b", INFO(0x206017, 0, 64 * 1024, 128, SPI_NOR_DUAL_READ),
+ PARAMS(xmc), CLK_MHZ_2X(80) },
+ { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
+ PARAMS(xmc), CLK_MHZ_2X(80) },
+ { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
+ PARAMS(xmc), CLK_MHZ_2X(80) },
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
@@ -1416,12 +1416,12 @@
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512,
- SPI_NOR_4B_OPCODES | SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(104) },
+ SPI_NOR_4B_OPCODES | SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
{ "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25fl127s/129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(108) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(108) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K
@@ -1442,7 +1442,7 @@
{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K
| SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "w25Q16jv-iq/s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(84) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(winbond), CLK_MHZ_2X(84) },
/* { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K
| SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, */
{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
@@ -1510,19 +1510,19 @@
| SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
{ "w25q64fv(spi)/w25q64jv_iq", INFO(0xef4017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25q128(b/f)v", INFO(0xef4018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(104) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
{ "w25q128jv_im", INFO(0xef7018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
#ifdef CONFIG_AUTOMOTIVE_GRADE
{ "w25q256(f/j)v", INFO(0xef4019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_QUAD_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
+ SECT_4K | SPI_NOR_DUAL_READ), PARAMS(winbond), CLK_MHZ_2X(80) },
#else
{ "w25q256(f/j)v", INFO(0xef4019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES), PARAMS(winbond), CLK_MHZ_2X(80) },
@@ -1544,7 +1544,7 @@
{ "w25q256jw-iq", INFO(0xef6019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES),
- PARAMS(winbond), CLK_MHZ_2X(133) },
+ PARAMS(winbond), CLK_MHZ_2X(80) },
/* Catalyst / On Semiconductor -- non-JEDEC */
{ "cat25c11", CAT25_INFO(16, 8, 16, 1, SPI_NOR_NO_ERASE
@@ -1559,42 +1559,42 @@
| SPI_NOR_NO_FR) },
/* Paragon 3.3V */
{ "pn25f16s", INFO(0xe04015, 0, 64 * 1024, 32,
- SPI_NOR_QUAD_READ), PARAMS(paragon), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(paragon), CLK_MHZ_2X(80) },
{ "pn25f32s", INFO(0xe04016, 0, 64 * 1024, 64,
- SPI_NOR_QUAD_READ), PARAMS(paragon), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(paragon), CLK_MHZ_2X(80) },
/* XTX */
{ "xt25f16bssigu", INFO(0x0b4015, 0, 64 * 1024, 32,
- SPI_NOR_QUAD_READ), PARAMS(xtx), CLK_MHZ_2X(120) },
+ SPI_NOR_DUAL_READ), PARAMS(xtx), CLK_MHZ_2X(80) },
{ "xt25f32bssigu-s", INFO(0x0b4016, 0, 64 * 1024, 64,
- SPI_NOR_QUAD_READ), PARAMS(xtx), CLK_MHZ_2X(120) },
+ SPI_NOR_DUAL_READ), PARAMS(xtx), CLK_MHZ_2X(80) },
{ "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
+ SPI_NOR_DUAL_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
{ "xt25f64b", INFO(0x0b4017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
+ SPI_NOR_DUAL_READ), PARAMS(xtx), CLK_MHZ_2X(70) },
/*puya 3.3V */
{"p25q128h", INFO(0x856018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(puya), CLK_MHZ_2X(104) },
+ SPI_NOR_DUAL_READ), PARAMS(puya), CLK_MHZ_2X(80) },
/* FM 3.3v */
{ "FM25Q64-SOB-T-G",INFO(0xa14017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
{ "FM25Q128-SOB-T-G",INFO(0xa14018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
/* HUAHONG 3.3v */
{ "H25S64",INFO(0x684017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
{ "H25S128",INFO(0x684018, 0, 64 * 1024, 256,
- SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
{ "ZB25VQ64A",INFO(0x5e4017, 0, 64 * 1024, 128,
- SPI_NOR_QUAD_READ), PARAMS(spansion), CLK_MHZ_2X(104) },
+ SPI_NOR_DUAL_READ), PARAMS(spansion), CLK_MHZ_2X(80) },
/* SiliconKaiser 3.3v */
{ "sk25p128", INFO(0x256018, 0, 64 * 1024, 256), PARAMS(xtx), CLK_MHZ_2X(70) },
@@ -2258,7 +2258,6 @@
switch (JEDEC_MFR(info)) {
case SNOR_MFR_GD:
case SNOR_MFR_FM:
- case SNOR_MFR_XTX:
case SNOR_MFR_ESMT:
case SNOR_MFR_EON:
case SNOR_MFR_SPANSION:
@@ -2273,12 +2272,17 @@
nor->level = bsp_bp_to_level(nor, info, BP_NUM_4);
break;
case SNOR_MFR_MACRONIX:
+
/* BP bit convert to lock level */
if (chipsize <= _8M)
nor->level = bsp_bp_to_level(nor, info, BP_NUM_3);
else
nor->level = bsp_bp_to_level(nor, info, BP_NUM_4);
break;
+ case SNOR_MFR_XTX:
+ /* BP bit convert to lock level */
+ nor->level = bsp_bp_to_level(nor, info, BP_NUM_4);
+ break;
default:
goto usage;
}