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Remove broken linked patches

pull/398/head
Dmitry Ilyin 2022-08-22 11:42:30 +03:00
parent 3ee469fb97
commit 191e8fd91e
24 changed files with 0 additions and 1896 deletions
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79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm-boot-dts-include-dt-bindings-clock-gk7202v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7202V300_CLOCK_H
+#define __DTS_GK7202V300_CLOCK_H
+
+/* clk in GK7202V300 CRG */
+/* fixed rate clocks */
+#define GK7202V300_FIXED_100K 1
+#define GK7202V300_FIXED_400K 2
+#define GK7202V300_FIXED_3M 3
+#define GK7202V300_FIXED_6M 4
+#define GK7202V300_FIXED_12M 5
+#define GK7202V300_FIXED_24M 6
+#define GK7202V300_FIXED_25M 7
+#define GK7202V300_FIXED_50M 8
+#define GK7202V300_FIXED_83P3M 9
+#define GK7202V300_FIXED_90M 10
+#define GK7202V300_FIXED_100M 11
+#define GK7202V300_FIXED_112M 12
+#define GK7202V300_FIXED_125M 13
+#define GK7202V300_FIXED_148P5M 14
+#define GK7202V300_FIXED_150M 15
+#define GK7202V300_FIXED_200M 16
+#define GK7202V300_FIXED_250M 17
+#define GK7202V300_FIXED_300M 18
+#define GK7202V300_FIXED_324M 19
+#define GK7202V300_FIXED_342M 20
+#define GK7202V300_FIXED_375M 21
+#define GK7202V300_FIXED_400M 22
+#define GK7202V300_FIXED_448M 23
+#define GK7202V300_FIXED_500M 24
+#define GK7202V300_FIXED_540M 25
+#define GK7202V300_FIXED_600M 26
+#define GK7202V300_FIXED_750M 27
+#define GK7202V300_FIXED_1000M 28
+#define GK7202V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7202V300_SYSAXI_CLK 30
+#define GK7202V300_SYSAPB_CLK 31
+#define GK7202V300_FMC_MUX 32
+#define GK7202V300_UART_MUX 33
+#define GK7202V300_MMC0_MUX 34
+#define GK7202V300_MMC1_MUX 35
+#define GK7202V300_MMC2_MUX 36
+#define GK7202V300_ETH_MUX 37
+#define GK7202V300_USB2_MUX 80
+/* gate clocks */
+#define GK7202V300_UART0_CLK 40
+#define GK7202V300_UART1_CLK 41
+#define GK7202V300_UART2_CLK 42
+#define GK7202V300_FMC_CLK 43
+#define GK7202V300_ETH0_CLK 44
+#define GK7202V300_EDMAC_AXICLK 45
+#define GK7202V300_EDMAC_CLK 46
+#define GK7202V300_SPI0_CLK 48
+#define GK7202V300_SPI1_CLK 49
+#define GK7202V300_MMC0_CLK 50
+#define GK7202V300_MMC1_CLK 51
+#define GK7202V300_MMC2_CLK 52
+#define GK7202V300_I2C0_CLK 53
+#define GK7202V300_I2C1_CLK 54
+#define GK7202V300_I2C2_CLK 55
+#define GK7202V300_USB2_BUS_CLK 81
+#define GK7202V300_USB2_REF_CLK 82
+#define GK7202V300_USB2_UTMI_CLK 83
+#define GK7202V300_USB2_PHY_APB_CLK 84
+#define GK7202V300_USB2_PHY_PLL_CLK 85
+#define GK7202V300_USB2_PHY_XO_CLK 86
+
+#define GK7202V300_NR_CLKS 256
+#define GK7202V300_NR_RSTS 256
+
+#endif /* __DTS_GK7202V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm-boot-dts-include-dt-bindings-clock-gk7205v200-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V200_CLOCK_H
+#define __DTS_GK7205V200_CLOCK_H
+
+/* clk in GK7205V200 CRG */
+/* fixed rate clocks */
+#define GK7205V200_FIXED_100K 1
+#define GK7205V200_FIXED_400K 2
+#define GK7205V200_FIXED_3M 3
+#define GK7205V200_FIXED_6M 4
+#define GK7205V200_FIXED_12M 5
+#define GK7205V200_FIXED_24M 6
+#define GK7205V200_FIXED_25M 7
+#define GK7205V200_FIXED_50M 8
+#define GK7205V200_FIXED_83P3M 9
+#define GK7205V200_FIXED_90M 10
+#define GK7205V200_FIXED_100M 11
+#define GK7205V200_FIXED_112M 12
+#define GK7205V200_FIXED_125M 13
+#define GK7205V200_FIXED_148P5M 14
+#define GK7205V200_FIXED_150M 15
+#define GK7205V200_FIXED_200M 16
+#define GK7205V200_FIXED_250M 17
+#define GK7205V200_FIXED_300M 18
+#define GK7205V200_FIXED_324M 19
+#define GK7205V200_FIXED_342M 20
+#define GK7205V200_FIXED_375M 21
+#define GK7205V200_FIXED_400M 22
+#define GK7205V200_FIXED_448M 23
+#define GK7205V200_FIXED_500M 24
+#define GK7205V200_FIXED_540M 25
+#define GK7205V200_FIXED_600M 26
+#define GK7205V200_FIXED_750M 27
+#define GK7205V200_FIXED_1000M 28
+#define GK7205V200_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V200_SYSAXI_CLK 30
+#define GK7205V200_SYSAPB_CLK 31
+#define GK7205V200_FMC_MUX 32
+#define GK7205V200_UART_MUX 33
+#define GK7205V200_MMC0_MUX 34
+#define GK7205V200_MMC1_MUX 35
+#define GK7205V200_MMC2_MUX 36
+#define GK7205V200_ETH_MUX 37
+#define GK7205V200_USB2_MUX 80
+/* gate clocks */
+#define GK7205V200_UART0_CLK 40
+#define GK7205V200_UART1_CLK 41
+#define GK7205V200_UART2_CLK 42
+#define GK7205V200_FMC_CLK 43
+#define GK7205V200_ETH0_CLK 44
+#define GK7205V200_EDMAC_AXICLK 45
+#define GK7205V200_EDMAC_CLK 46
+#define GK7205V200_SPI0_CLK 48
+#define GK7205V200_SPI1_CLK 49
+#define GK7205V200_MMC0_CLK 50
+#define GK7205V200_MMC1_CLK 51
+#define GK7205V200_MMC2_CLK 52
+#define GK7205V200_I2C0_CLK 53
+#define GK7205V200_I2C1_CLK 54
+#define GK7205V200_I2C2_CLK 55
+#define GK7205V200_USB2_BUS_CLK 81
+#define GK7205V200_USB2_REF_CLK 82
+#define GK7205V200_USB2_UTMI_CLK 83
+#define GK7205V200_USB2_PHY_APB_CLK 84
+#define GK7205V200_USB2_PHY_PLL_CLK 85
+#define GK7205V200_USB2_PHY_XO_CLK 86
+
+#define GK7205V200_NR_CLKS 256
+#define GK7205V200_NR_RSTS 256
+
+#endif /* __DTS_GK7205V200_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm-boot-dts-include-dt-bindings-clock-gk7205v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V300_CLOCK_H
+#define __DTS_GK7205V300_CLOCK_H
+
+/* clk in GK7205V300 CRG */
+/* fixed rate clocks */
+#define GK7205V300_FIXED_100K 1
+#define GK7205V300_FIXED_400K 2
+#define GK7205V300_FIXED_3M 3
+#define GK7205V300_FIXED_6M 4
+#define GK7205V300_FIXED_12M 5
+#define GK7205V300_FIXED_24M 6
+#define GK7205V300_FIXED_25M 7
+#define GK7205V300_FIXED_50M 8
+#define GK7205V300_FIXED_83P3M 9
+#define GK7205V300_FIXED_90M 10
+#define GK7205V300_FIXED_100M 11
+#define GK7205V300_FIXED_112M 12
+#define GK7205V300_FIXED_125M 13
+#define GK7205V300_FIXED_148P5M 14
+#define GK7205V300_FIXED_150M 15
+#define GK7205V300_FIXED_200M 16
+#define GK7205V300_FIXED_250M 17
+#define GK7205V300_FIXED_300M 18
+#define GK7205V300_FIXED_324M 19
+#define GK7205V300_FIXED_342M 20
+#define GK7205V300_FIXED_375M 21
+#define GK7205V300_FIXED_400M 22
+#define GK7205V300_FIXED_448M 23
+#define GK7205V300_FIXED_500M 24
+#define GK7205V300_FIXED_540M 25
+#define GK7205V300_FIXED_600M 26
+#define GK7205V300_FIXED_750M 27
+#define GK7205V300_FIXED_1000M 28
+#define GK7205V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V300_SYSAXI_CLK 30
+#define GK7205V300_SYSAPB_CLK 31
+#define GK7205V300_FMC_MUX 32
+#define GK7205V300_UART_MUX 33
+#define GK7205V300_MMC0_MUX 34
+#define GK7205V300_MMC1_MUX 35
+#define GK7205V300_MMC2_MUX 36
+#define GK7205V300_ETH_MUX 37
+#define GK7205V300_USB2_MUX 80
+/* gate clocks */
+#define GK7205V300_UART0_CLK 40
+#define GK7205V300_UART1_CLK 41
+#define GK7205V300_UART2_CLK 42
+#define GK7205V300_FMC_CLK 43
+#define GK7205V300_ETH0_CLK 44
+#define GK7205V300_EDMAC_AXICLK 45
+#define GK7205V300_EDMAC_CLK 46
+#define GK7205V300_SPI0_CLK 48
+#define GK7205V300_SPI1_CLK 49
+#define GK7205V300_MMC0_CLK 50
+#define GK7205V300_MMC1_CLK 51
+#define GK7205V300_MMC2_CLK 52
+#define GK7205V300_I2C0_CLK 53
+#define GK7205V300_I2C1_CLK 54
+#define GK7205V300_I2C2_CLK 55
+#define GK7205V300_USB2_BUS_CLK 81
+#define GK7205V300_USB2_REF_CLK 82
+#define GK7205V300_USB2_UTMI_CLK 83
+#define GK7205V300_USB2_PHY_APB_CLK 84
+#define GK7205V300_USB2_PHY_PLL_CLK 85
+#define GK7205V300_USB2_PHY_XO_CLK 86
+
+#define GK7205V300_NR_CLKS 256
+#define GK7205V300_NR_RSTS 256
+
+#endif /* __DTS_GK7205V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm-boot-dts-include-dt-bindings-clock-gk7605v100-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7605V100_CLOCK_H
+#define __DTS_GK7605V100_CLOCK_H
+
+/* clk in GK7605V100 CRG */
+/* fixed rate clocks */
+#define GK7605V100_FIXED_100K 1
+#define GK7605V100_FIXED_400K 2
+#define GK7605V100_FIXED_3M 3
+#define GK7605V100_FIXED_6M 4
+#define GK7605V100_FIXED_12M 5
+#define GK7605V100_FIXED_24M 6
+#define GK7605V100_FIXED_25M 7
+#define GK7605V100_FIXED_50M 8
+#define GK7605V100_FIXED_83P3M 9
+#define GK7605V100_FIXED_90M 10
+#define GK7605V100_FIXED_100M 11
+#define GK7605V100_FIXED_112M 12
+#define GK7605V100_FIXED_125M 13
+#define GK7605V100_FIXED_148P5M 14
+#define GK7605V100_FIXED_150M 15
+#define GK7605V100_FIXED_200M 16
+#define GK7605V100_FIXED_250M 17
+#define GK7605V100_FIXED_300M 18
+#define GK7605V100_FIXED_324M 19
+#define GK7605V100_FIXED_342M 20
+#define GK7605V100_FIXED_375M 21
+#define GK7605V100_FIXED_400M 22
+#define GK7605V100_FIXED_448M 23
+#define GK7605V100_FIXED_500M 24
+#define GK7605V100_FIXED_540M 25
+#define GK7605V100_FIXED_600M 26
+#define GK7605V100_FIXED_750M 27
+#define GK7605V100_FIXED_1000M 28
+#define GK7605V100_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7605V100_SYSAXI_CLK 30
+#define GK7605V100_SYSAPB_CLK 31
+#define GK7605V100_FMC_MUX 32
+#define GK7605V100_UART_MUX 33
+#define GK7605V100_MMC0_MUX 34
+#define GK7605V100_MMC1_MUX 35
+#define GK7605V100_MMC2_MUX 36
+#define GK7605V100_ETH_MUX 37
+#define GK7605V100_USB2_MUX 80
+/* gate clocks */
+#define GK7605V100_UART0_CLK 40
+#define GK7605V100_UART1_CLK 41
+#define GK7605V100_UART2_CLK 42
+#define GK7605V100_FMC_CLK 43
+#define GK7605V100_ETH0_CLK 44
+#define GK7605V100_EDMAC_AXICLK 45
+#define GK7605V100_EDMAC_CLK 46
+#define GK7605V100_SPI0_CLK 48
+#define GK7605V100_SPI1_CLK 49
+#define GK7605V100_MMC0_CLK 50
+#define GK7605V100_MMC1_CLK 51
+#define GK7605V100_MMC2_CLK 52
+#define GK7605V100_I2C0_CLK 53
+#define GK7605V100_I2C1_CLK 54
+#define GK7605V100_I2C2_CLK 55
+#define GK7605V100_USB2_BUS_CLK 81
+#define GK7605V100_USB2_REF_CLK 82
+#define GK7605V100_USB2_UTMI_CLK 83
+#define GK7605V100_USB2_PHY_APB_CLK 84
+#define GK7605V100_USB2_PHY_PLL_CLK 85
+#define GK7605V100_USB2_PHY_XO_CLK 86
+
+#define GK7605V100_NR_CLKS 256
+#define GK7605V100_NR_RSTS 256
+
+#endif /* __DTS_GK7605V100_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm64-boot-dts-include-dt-bindings-clock-gk7202v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7202V300_CLOCK_H
+#define __DTS_GK7202V300_CLOCK_H
+
+/* clk in GK7202V300 CRG */
+/* fixed rate clocks */
+#define GK7202V300_FIXED_100K 1
+#define GK7202V300_FIXED_400K 2
+#define GK7202V300_FIXED_3M 3
+#define GK7202V300_FIXED_6M 4
+#define GK7202V300_FIXED_12M 5
+#define GK7202V300_FIXED_24M 6
+#define GK7202V300_FIXED_25M 7
+#define GK7202V300_FIXED_50M 8
+#define GK7202V300_FIXED_83P3M 9
+#define GK7202V300_FIXED_90M 10
+#define GK7202V300_FIXED_100M 11
+#define GK7202V300_FIXED_112M 12
+#define GK7202V300_FIXED_125M 13
+#define GK7202V300_FIXED_148P5M 14
+#define GK7202V300_FIXED_150M 15
+#define GK7202V300_FIXED_200M 16
+#define GK7202V300_FIXED_250M 17
+#define GK7202V300_FIXED_300M 18
+#define GK7202V300_FIXED_324M 19
+#define GK7202V300_FIXED_342M 20
+#define GK7202V300_FIXED_375M 21
+#define GK7202V300_FIXED_400M 22
+#define GK7202V300_FIXED_448M 23
+#define GK7202V300_FIXED_500M 24
+#define GK7202V300_FIXED_540M 25
+#define GK7202V300_FIXED_600M 26
+#define GK7202V300_FIXED_750M 27
+#define GK7202V300_FIXED_1000M 28
+#define GK7202V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7202V300_SYSAXI_CLK 30
+#define GK7202V300_SYSAPB_CLK 31
+#define GK7202V300_FMC_MUX 32
+#define GK7202V300_UART_MUX 33
+#define GK7202V300_MMC0_MUX 34
+#define GK7202V300_MMC1_MUX 35
+#define GK7202V300_MMC2_MUX 36
+#define GK7202V300_ETH_MUX 37
+#define GK7202V300_USB2_MUX 80
+/* gate clocks */
+#define GK7202V300_UART0_CLK 40
+#define GK7202V300_UART1_CLK 41
+#define GK7202V300_UART2_CLK 42
+#define GK7202V300_FMC_CLK 43
+#define GK7202V300_ETH0_CLK 44
+#define GK7202V300_EDMAC_AXICLK 45
+#define GK7202V300_EDMAC_CLK 46
+#define GK7202V300_SPI0_CLK 48
+#define GK7202V300_SPI1_CLK 49
+#define GK7202V300_MMC0_CLK 50
+#define GK7202V300_MMC1_CLK 51
+#define GK7202V300_MMC2_CLK 52
+#define GK7202V300_I2C0_CLK 53
+#define GK7202V300_I2C1_CLK 54
+#define GK7202V300_I2C2_CLK 55
+#define GK7202V300_USB2_BUS_CLK 81
+#define GK7202V300_USB2_REF_CLK 82
+#define GK7202V300_USB2_UTMI_CLK 83
+#define GK7202V300_USB2_PHY_APB_CLK 84
+#define GK7202V300_USB2_PHY_PLL_CLK 85
+#define GK7202V300_USB2_PHY_XO_CLK 86
+
+#define GK7202V300_NR_CLKS 256
+#define GK7202V300_NR_RSTS 256
+
+#endif /* __DTS_GK7202V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm64-boot-dts-include-dt-bindings-clock-gk7205v200-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V200_CLOCK_H
+#define __DTS_GK7205V200_CLOCK_H
+
+/* clk in GK7205V200 CRG */
+/* fixed rate clocks */
+#define GK7205V200_FIXED_100K 1
+#define GK7205V200_FIXED_400K 2
+#define GK7205V200_FIXED_3M 3
+#define GK7205V200_FIXED_6M 4
+#define GK7205V200_FIXED_12M 5
+#define GK7205V200_FIXED_24M 6
+#define GK7205V200_FIXED_25M 7
+#define GK7205V200_FIXED_50M 8
+#define GK7205V200_FIXED_83P3M 9
+#define GK7205V200_FIXED_90M 10
+#define GK7205V200_FIXED_100M 11
+#define GK7205V200_FIXED_112M 12
+#define GK7205V200_FIXED_125M 13
+#define GK7205V200_FIXED_148P5M 14
+#define GK7205V200_FIXED_150M 15
+#define GK7205V200_FIXED_200M 16
+#define GK7205V200_FIXED_250M 17
+#define GK7205V200_FIXED_300M 18
+#define GK7205V200_FIXED_324M 19
+#define GK7205V200_FIXED_342M 20
+#define GK7205V200_FIXED_375M 21
+#define GK7205V200_FIXED_400M 22
+#define GK7205V200_FIXED_448M 23
+#define GK7205V200_FIXED_500M 24
+#define GK7205V200_FIXED_540M 25
+#define GK7205V200_FIXED_600M 26
+#define GK7205V200_FIXED_750M 27
+#define GK7205V200_FIXED_1000M 28
+#define GK7205V200_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V200_SYSAXI_CLK 30
+#define GK7205V200_SYSAPB_CLK 31
+#define GK7205V200_FMC_MUX 32
+#define GK7205V200_UART_MUX 33
+#define GK7205V200_MMC0_MUX 34
+#define GK7205V200_MMC1_MUX 35
+#define GK7205V200_MMC2_MUX 36
+#define GK7205V200_ETH_MUX 37
+#define GK7205V200_USB2_MUX 80
+/* gate clocks */
+#define GK7205V200_UART0_CLK 40
+#define GK7205V200_UART1_CLK 41
+#define GK7205V200_UART2_CLK 42
+#define GK7205V200_FMC_CLK 43
+#define GK7205V200_ETH0_CLK 44
+#define GK7205V200_EDMAC_AXICLK 45
+#define GK7205V200_EDMAC_CLK 46
+#define GK7205V200_SPI0_CLK 48
+#define GK7205V200_SPI1_CLK 49
+#define GK7205V200_MMC0_CLK 50
+#define GK7205V200_MMC1_CLK 51
+#define GK7205V200_MMC2_CLK 52
+#define GK7205V200_I2C0_CLK 53
+#define GK7205V200_I2C1_CLK 54
+#define GK7205V200_I2C2_CLK 55
+#define GK7205V200_USB2_BUS_CLK 81
+#define GK7205V200_USB2_REF_CLK 82
+#define GK7205V200_USB2_UTMI_CLK 83
+#define GK7205V200_USB2_PHY_APB_CLK 84
+#define GK7205V200_USB2_PHY_PLL_CLK 85
+#define GK7205V200_USB2_PHY_XO_CLK 86
+
+#define GK7205V200_NR_CLKS 256
+#define GK7205V200_NR_RSTS 256
+
+#endif /* __DTS_GK7205V200_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm64-boot-dts-include-dt-bindings-clock-gk7205v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V300_CLOCK_H
+#define __DTS_GK7205V300_CLOCK_H
+
+/* clk in GK7205V300 CRG */
+/* fixed rate clocks */
+#define GK7205V300_FIXED_100K 1
+#define GK7205V300_FIXED_400K 2
+#define GK7205V300_FIXED_3M 3
+#define GK7205V300_FIXED_6M 4
+#define GK7205V300_FIXED_12M 5
+#define GK7205V300_FIXED_24M 6
+#define GK7205V300_FIXED_25M 7
+#define GK7205V300_FIXED_50M 8
+#define GK7205V300_FIXED_83P3M 9
+#define GK7205V300_FIXED_90M 10
+#define GK7205V300_FIXED_100M 11
+#define GK7205V300_FIXED_112M 12
+#define GK7205V300_FIXED_125M 13
+#define GK7205V300_FIXED_148P5M 14
+#define GK7205V300_FIXED_150M 15
+#define GK7205V300_FIXED_200M 16
+#define GK7205V300_FIXED_250M 17
+#define GK7205V300_FIXED_300M 18
+#define GK7205V300_FIXED_324M 19
+#define GK7205V300_FIXED_342M 20
+#define GK7205V300_FIXED_375M 21
+#define GK7205V300_FIXED_400M 22
+#define GK7205V300_FIXED_448M 23
+#define GK7205V300_FIXED_500M 24
+#define GK7205V300_FIXED_540M 25
+#define GK7205V300_FIXED_600M 26
+#define GK7205V300_FIXED_750M 27
+#define GK7205V300_FIXED_1000M 28
+#define GK7205V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V300_SYSAXI_CLK 30
+#define GK7205V300_SYSAPB_CLK 31
+#define GK7205V300_FMC_MUX 32
+#define GK7205V300_UART_MUX 33
+#define GK7205V300_MMC0_MUX 34
+#define GK7205V300_MMC1_MUX 35
+#define GK7205V300_MMC2_MUX 36
+#define GK7205V300_ETH_MUX 37
+#define GK7205V300_USB2_MUX 80
+/* gate clocks */
+#define GK7205V300_UART0_CLK 40
+#define GK7205V300_UART1_CLK 41
+#define GK7205V300_UART2_CLK 42
+#define GK7205V300_FMC_CLK 43
+#define GK7205V300_ETH0_CLK 44
+#define GK7205V300_EDMAC_AXICLK 45
+#define GK7205V300_EDMAC_CLK 46
+#define GK7205V300_SPI0_CLK 48
+#define GK7205V300_SPI1_CLK 49
+#define GK7205V300_MMC0_CLK 50
+#define GK7205V300_MMC1_CLK 51
+#define GK7205V300_MMC2_CLK 52
+#define GK7205V300_I2C0_CLK 53
+#define GK7205V300_I2C1_CLK 54
+#define GK7205V300_I2C2_CLK 55
+#define GK7205V300_USB2_BUS_CLK 81
+#define GK7205V300_USB2_REF_CLK 82
+#define GK7205V300_USB2_UTMI_CLK 83
+#define GK7205V300_USB2_PHY_APB_CLK 84
+#define GK7205V300_USB2_PHY_PLL_CLK 85
+#define GK7205V300_USB2_PHY_XO_CLK 86
+
+#define GK7205V300_NR_CLKS 256
+#define GK7205V300_NR_RSTS 256
+
+#endif /* __DTS_GK7205V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-arm64-boot-dts-include-dt-bindings-clock-gk7605v100-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/arm64/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/arm64/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7605V100_CLOCK_H
+#define __DTS_GK7605V100_CLOCK_H
+
+/* clk in GK7605V100 CRG */
+/* fixed rate clocks */
+#define GK7605V100_FIXED_100K 1
+#define GK7605V100_FIXED_400K 2
+#define GK7605V100_FIXED_3M 3
+#define GK7605V100_FIXED_6M 4
+#define GK7605V100_FIXED_12M 5
+#define GK7605V100_FIXED_24M 6
+#define GK7605V100_FIXED_25M 7
+#define GK7605V100_FIXED_50M 8
+#define GK7605V100_FIXED_83P3M 9
+#define GK7605V100_FIXED_90M 10
+#define GK7605V100_FIXED_100M 11
+#define GK7605V100_FIXED_112M 12
+#define GK7605V100_FIXED_125M 13
+#define GK7605V100_FIXED_148P5M 14
+#define GK7605V100_FIXED_150M 15
+#define GK7605V100_FIXED_200M 16
+#define GK7605V100_FIXED_250M 17
+#define GK7605V100_FIXED_300M 18
+#define GK7605V100_FIXED_324M 19
+#define GK7605V100_FIXED_342M 20
+#define GK7605V100_FIXED_375M 21
+#define GK7605V100_FIXED_400M 22
+#define GK7605V100_FIXED_448M 23
+#define GK7605V100_FIXED_500M 24
+#define GK7605V100_FIXED_540M 25
+#define GK7605V100_FIXED_600M 26
+#define GK7605V100_FIXED_750M 27
+#define GK7605V100_FIXED_1000M 28
+#define GK7605V100_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7605V100_SYSAXI_CLK 30
+#define GK7605V100_SYSAPB_CLK 31
+#define GK7605V100_FMC_MUX 32
+#define GK7605V100_UART_MUX 33
+#define GK7605V100_MMC0_MUX 34
+#define GK7605V100_MMC1_MUX 35
+#define GK7605V100_MMC2_MUX 36
+#define GK7605V100_ETH_MUX 37
+#define GK7605V100_USB2_MUX 80
+/* gate clocks */
+#define GK7605V100_UART0_CLK 40
+#define GK7605V100_UART1_CLK 41
+#define GK7605V100_UART2_CLK 42
+#define GK7605V100_FMC_CLK 43
+#define GK7605V100_ETH0_CLK 44
+#define GK7605V100_EDMAC_AXICLK 45
+#define GK7605V100_EDMAC_CLK 46
+#define GK7605V100_SPI0_CLK 48
+#define GK7605V100_SPI1_CLK 49
+#define GK7605V100_MMC0_CLK 50
+#define GK7605V100_MMC1_CLK 51
+#define GK7605V100_MMC2_CLK 52
+#define GK7605V100_I2C0_CLK 53
+#define GK7605V100_I2C1_CLK 54
+#define GK7605V100_I2C2_CLK 55
+#define GK7605V100_USB2_BUS_CLK 81
+#define GK7605V100_USB2_REF_CLK 82
+#define GK7605V100_USB2_UTMI_CLK 83
+#define GK7605V100_USB2_PHY_APB_CLK 84
+#define GK7605V100_USB2_PHY_PLL_CLK 85
+#define GK7605V100_USB2_PHY_XO_CLK 86
+
+#define GK7605V100_NR_CLKS 256
+#define GK7605V100_NR_RSTS 256
+
+#endif /* __DTS_GK7605V100_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-cris-boot-dts-include-dt-bindings-clock-gk7202v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7202V300_CLOCK_H
+#define __DTS_GK7202V300_CLOCK_H
+
+/* clk in GK7202V300 CRG */
+/* fixed rate clocks */
+#define GK7202V300_FIXED_100K 1
+#define GK7202V300_FIXED_400K 2
+#define GK7202V300_FIXED_3M 3
+#define GK7202V300_FIXED_6M 4
+#define GK7202V300_FIXED_12M 5
+#define GK7202V300_FIXED_24M 6
+#define GK7202V300_FIXED_25M 7
+#define GK7202V300_FIXED_50M 8
+#define GK7202V300_FIXED_83P3M 9
+#define GK7202V300_FIXED_90M 10
+#define GK7202V300_FIXED_100M 11
+#define GK7202V300_FIXED_112M 12
+#define GK7202V300_FIXED_125M 13
+#define GK7202V300_FIXED_148P5M 14
+#define GK7202V300_FIXED_150M 15
+#define GK7202V300_FIXED_200M 16
+#define GK7202V300_FIXED_250M 17
+#define GK7202V300_FIXED_300M 18
+#define GK7202V300_FIXED_324M 19
+#define GK7202V300_FIXED_342M 20
+#define GK7202V300_FIXED_375M 21
+#define GK7202V300_FIXED_400M 22
+#define GK7202V300_FIXED_448M 23
+#define GK7202V300_FIXED_500M 24
+#define GK7202V300_FIXED_540M 25
+#define GK7202V300_FIXED_600M 26
+#define GK7202V300_FIXED_750M 27
+#define GK7202V300_FIXED_1000M 28
+#define GK7202V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7202V300_SYSAXI_CLK 30
+#define GK7202V300_SYSAPB_CLK 31
+#define GK7202V300_FMC_MUX 32
+#define GK7202V300_UART_MUX 33
+#define GK7202V300_MMC0_MUX 34
+#define GK7202V300_MMC1_MUX 35
+#define GK7202V300_MMC2_MUX 36
+#define GK7202V300_ETH_MUX 37
+#define GK7202V300_USB2_MUX 80
+/* gate clocks */
+#define GK7202V300_UART0_CLK 40
+#define GK7202V300_UART1_CLK 41
+#define GK7202V300_UART2_CLK 42
+#define GK7202V300_FMC_CLK 43
+#define GK7202V300_ETH0_CLK 44
+#define GK7202V300_EDMAC_AXICLK 45
+#define GK7202V300_EDMAC_CLK 46
+#define GK7202V300_SPI0_CLK 48
+#define GK7202V300_SPI1_CLK 49
+#define GK7202V300_MMC0_CLK 50
+#define GK7202V300_MMC1_CLK 51
+#define GK7202V300_MMC2_CLK 52
+#define GK7202V300_I2C0_CLK 53
+#define GK7202V300_I2C1_CLK 54
+#define GK7202V300_I2C2_CLK 55
+#define GK7202V300_USB2_BUS_CLK 81
+#define GK7202V300_USB2_REF_CLK 82
+#define GK7202V300_USB2_UTMI_CLK 83
+#define GK7202V300_USB2_PHY_APB_CLK 84
+#define GK7202V300_USB2_PHY_PLL_CLK 85
+#define GK7202V300_USB2_PHY_XO_CLK 86
+
+#define GK7202V300_NR_CLKS 256
+#define GK7202V300_NR_RSTS 256
+
+#endif /* __DTS_GK7202V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-cris-boot-dts-include-dt-bindings-clock-gk7205v200-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V200_CLOCK_H
+#define __DTS_GK7205V200_CLOCK_H
+
+/* clk in GK7205V200 CRG */
+/* fixed rate clocks */
+#define GK7205V200_FIXED_100K 1
+#define GK7205V200_FIXED_400K 2
+#define GK7205V200_FIXED_3M 3
+#define GK7205V200_FIXED_6M 4
+#define GK7205V200_FIXED_12M 5
+#define GK7205V200_FIXED_24M 6
+#define GK7205V200_FIXED_25M 7
+#define GK7205V200_FIXED_50M 8
+#define GK7205V200_FIXED_83P3M 9
+#define GK7205V200_FIXED_90M 10
+#define GK7205V200_FIXED_100M 11
+#define GK7205V200_FIXED_112M 12
+#define GK7205V200_FIXED_125M 13
+#define GK7205V200_FIXED_148P5M 14
+#define GK7205V200_FIXED_150M 15
+#define GK7205V200_FIXED_200M 16
+#define GK7205V200_FIXED_250M 17
+#define GK7205V200_FIXED_300M 18
+#define GK7205V200_FIXED_324M 19
+#define GK7205V200_FIXED_342M 20
+#define GK7205V200_FIXED_375M 21
+#define GK7205V200_FIXED_400M 22
+#define GK7205V200_FIXED_448M 23
+#define GK7205V200_FIXED_500M 24
+#define GK7205V200_FIXED_540M 25
+#define GK7205V200_FIXED_600M 26
+#define GK7205V200_FIXED_750M 27
+#define GK7205V200_FIXED_1000M 28
+#define GK7205V200_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V200_SYSAXI_CLK 30
+#define GK7205V200_SYSAPB_CLK 31
+#define GK7205V200_FMC_MUX 32
+#define GK7205V200_UART_MUX 33
+#define GK7205V200_MMC0_MUX 34
+#define GK7205V200_MMC1_MUX 35
+#define GK7205V200_MMC2_MUX 36
+#define GK7205V200_ETH_MUX 37
+#define GK7205V200_USB2_MUX 80
+/* gate clocks */
+#define GK7205V200_UART0_CLK 40
+#define GK7205V200_UART1_CLK 41
+#define GK7205V200_UART2_CLK 42
+#define GK7205V200_FMC_CLK 43
+#define GK7205V200_ETH0_CLK 44
+#define GK7205V200_EDMAC_AXICLK 45
+#define GK7205V200_EDMAC_CLK 46
+#define GK7205V200_SPI0_CLK 48
+#define GK7205V200_SPI1_CLK 49
+#define GK7205V200_MMC0_CLK 50
+#define GK7205V200_MMC1_CLK 51
+#define GK7205V200_MMC2_CLK 52
+#define GK7205V200_I2C0_CLK 53
+#define GK7205V200_I2C1_CLK 54
+#define GK7205V200_I2C2_CLK 55
+#define GK7205V200_USB2_BUS_CLK 81
+#define GK7205V200_USB2_REF_CLK 82
+#define GK7205V200_USB2_UTMI_CLK 83
+#define GK7205V200_USB2_PHY_APB_CLK 84
+#define GK7205V200_USB2_PHY_PLL_CLK 85
+#define GK7205V200_USB2_PHY_XO_CLK 86
+
+#define GK7205V200_NR_CLKS 256
+#define GK7205V200_NR_RSTS 256
+
+#endif /* __DTS_GK7205V200_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-cris-boot-dts-include-dt-bindings-clock-gk7205v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V300_CLOCK_H
+#define __DTS_GK7205V300_CLOCK_H
+
+/* clk in GK7205V300 CRG */
+/* fixed rate clocks */
+#define GK7205V300_FIXED_100K 1
+#define GK7205V300_FIXED_400K 2
+#define GK7205V300_FIXED_3M 3
+#define GK7205V300_FIXED_6M 4
+#define GK7205V300_FIXED_12M 5
+#define GK7205V300_FIXED_24M 6
+#define GK7205V300_FIXED_25M 7
+#define GK7205V300_FIXED_50M 8
+#define GK7205V300_FIXED_83P3M 9
+#define GK7205V300_FIXED_90M 10
+#define GK7205V300_FIXED_100M 11
+#define GK7205V300_FIXED_112M 12
+#define GK7205V300_FIXED_125M 13
+#define GK7205V300_FIXED_148P5M 14
+#define GK7205V300_FIXED_150M 15
+#define GK7205V300_FIXED_200M 16
+#define GK7205V300_FIXED_250M 17
+#define GK7205V300_FIXED_300M 18
+#define GK7205V300_FIXED_324M 19
+#define GK7205V300_FIXED_342M 20
+#define GK7205V300_FIXED_375M 21
+#define GK7205V300_FIXED_400M 22
+#define GK7205V300_FIXED_448M 23
+#define GK7205V300_FIXED_500M 24
+#define GK7205V300_FIXED_540M 25
+#define GK7205V300_FIXED_600M 26
+#define GK7205V300_FIXED_750M 27
+#define GK7205V300_FIXED_1000M 28
+#define GK7205V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V300_SYSAXI_CLK 30
+#define GK7205V300_SYSAPB_CLK 31
+#define GK7205V300_FMC_MUX 32
+#define GK7205V300_UART_MUX 33
+#define GK7205V300_MMC0_MUX 34
+#define GK7205V300_MMC1_MUX 35
+#define GK7205V300_MMC2_MUX 36
+#define GK7205V300_ETH_MUX 37
+#define GK7205V300_USB2_MUX 80
+/* gate clocks */
+#define GK7205V300_UART0_CLK 40
+#define GK7205V300_UART1_CLK 41
+#define GK7205V300_UART2_CLK 42
+#define GK7205V300_FMC_CLK 43
+#define GK7205V300_ETH0_CLK 44
+#define GK7205V300_EDMAC_AXICLK 45
+#define GK7205V300_EDMAC_CLK 46
+#define GK7205V300_SPI0_CLK 48
+#define GK7205V300_SPI1_CLK 49
+#define GK7205V300_MMC0_CLK 50
+#define GK7205V300_MMC1_CLK 51
+#define GK7205V300_MMC2_CLK 52
+#define GK7205V300_I2C0_CLK 53
+#define GK7205V300_I2C1_CLK 54
+#define GK7205V300_I2C2_CLK 55
+#define GK7205V300_USB2_BUS_CLK 81
+#define GK7205V300_USB2_REF_CLK 82
+#define GK7205V300_USB2_UTMI_CLK 83
+#define GK7205V300_USB2_PHY_APB_CLK 84
+#define GK7205V300_USB2_PHY_PLL_CLK 85
+#define GK7205V300_USB2_PHY_XO_CLK 86
+
+#define GK7205V300_NR_CLKS 256
+#define GK7205V300_NR_RSTS 256
+
+#endif /* __DTS_GK7205V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-cris-boot-dts-include-dt-bindings-clock-gk7605v100-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/cris/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/cris/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7605V100_CLOCK_H
+#define __DTS_GK7605V100_CLOCK_H
+
+/* clk in GK7605V100 CRG */
+/* fixed rate clocks */
+#define GK7605V100_FIXED_100K 1
+#define GK7605V100_FIXED_400K 2
+#define GK7605V100_FIXED_3M 3
+#define GK7605V100_FIXED_6M 4
+#define GK7605V100_FIXED_12M 5
+#define GK7605V100_FIXED_24M 6
+#define GK7605V100_FIXED_25M 7
+#define GK7605V100_FIXED_50M 8
+#define GK7605V100_FIXED_83P3M 9
+#define GK7605V100_FIXED_90M 10
+#define GK7605V100_FIXED_100M 11
+#define GK7605V100_FIXED_112M 12
+#define GK7605V100_FIXED_125M 13
+#define GK7605V100_FIXED_148P5M 14
+#define GK7605V100_FIXED_150M 15
+#define GK7605V100_FIXED_200M 16
+#define GK7605V100_FIXED_250M 17
+#define GK7605V100_FIXED_300M 18
+#define GK7605V100_FIXED_324M 19
+#define GK7605V100_FIXED_342M 20
+#define GK7605V100_FIXED_375M 21
+#define GK7605V100_FIXED_400M 22
+#define GK7605V100_FIXED_448M 23
+#define GK7605V100_FIXED_500M 24
+#define GK7605V100_FIXED_540M 25
+#define GK7605V100_FIXED_600M 26
+#define GK7605V100_FIXED_750M 27
+#define GK7605V100_FIXED_1000M 28
+#define GK7605V100_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7605V100_SYSAXI_CLK 30
+#define GK7605V100_SYSAPB_CLK 31
+#define GK7605V100_FMC_MUX 32
+#define GK7605V100_UART_MUX 33
+#define GK7605V100_MMC0_MUX 34
+#define GK7605V100_MMC1_MUX 35
+#define GK7605V100_MMC2_MUX 36
+#define GK7605V100_ETH_MUX 37
+#define GK7605V100_USB2_MUX 80
+/* gate clocks */
+#define GK7605V100_UART0_CLK 40
+#define GK7605V100_UART1_CLK 41
+#define GK7605V100_UART2_CLK 42
+#define GK7605V100_FMC_CLK 43
+#define GK7605V100_ETH0_CLK 44
+#define GK7605V100_EDMAC_AXICLK 45
+#define GK7605V100_EDMAC_CLK 46
+#define GK7605V100_SPI0_CLK 48
+#define GK7605V100_SPI1_CLK 49
+#define GK7605V100_MMC0_CLK 50
+#define GK7605V100_MMC1_CLK 51
+#define GK7605V100_MMC2_CLK 52
+#define GK7605V100_I2C0_CLK 53
+#define GK7605V100_I2C1_CLK 54
+#define GK7605V100_I2C2_CLK 55
+#define GK7605V100_USB2_BUS_CLK 81
+#define GK7605V100_USB2_REF_CLK 82
+#define GK7605V100_USB2_UTMI_CLK 83
+#define GK7605V100_USB2_PHY_APB_CLK 84
+#define GK7605V100_USB2_PHY_PLL_CLK 85
+#define GK7605V100_USB2_PHY_XO_CLK 86
+
+#define GK7605V100_NR_CLKS 256
+#define GK7605V100_NR_RSTS 256
+
+#endif /* __DTS_GK7605V100_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-metag-boot-dts-include-dt-bindings-clock-gk7202v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7202V300_CLOCK_H
+#define __DTS_GK7202V300_CLOCK_H
+
+/* clk in GK7202V300 CRG */
+/* fixed rate clocks */
+#define GK7202V300_FIXED_100K 1
+#define GK7202V300_FIXED_400K 2
+#define GK7202V300_FIXED_3M 3
+#define GK7202V300_FIXED_6M 4
+#define GK7202V300_FIXED_12M 5
+#define GK7202V300_FIXED_24M 6
+#define GK7202V300_FIXED_25M 7
+#define GK7202V300_FIXED_50M 8
+#define GK7202V300_FIXED_83P3M 9
+#define GK7202V300_FIXED_90M 10
+#define GK7202V300_FIXED_100M 11
+#define GK7202V300_FIXED_112M 12
+#define GK7202V300_FIXED_125M 13
+#define GK7202V300_FIXED_148P5M 14
+#define GK7202V300_FIXED_150M 15
+#define GK7202V300_FIXED_200M 16
+#define GK7202V300_FIXED_250M 17
+#define GK7202V300_FIXED_300M 18
+#define GK7202V300_FIXED_324M 19
+#define GK7202V300_FIXED_342M 20
+#define GK7202V300_FIXED_375M 21
+#define GK7202V300_FIXED_400M 22
+#define GK7202V300_FIXED_448M 23
+#define GK7202V300_FIXED_500M 24
+#define GK7202V300_FIXED_540M 25
+#define GK7202V300_FIXED_600M 26
+#define GK7202V300_FIXED_750M 27
+#define GK7202V300_FIXED_1000M 28
+#define GK7202V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7202V300_SYSAXI_CLK 30
+#define GK7202V300_SYSAPB_CLK 31
+#define GK7202V300_FMC_MUX 32
+#define GK7202V300_UART_MUX 33
+#define GK7202V300_MMC0_MUX 34
+#define GK7202V300_MMC1_MUX 35
+#define GK7202V300_MMC2_MUX 36
+#define GK7202V300_ETH_MUX 37
+#define GK7202V300_USB2_MUX 80
+/* gate clocks */
+#define GK7202V300_UART0_CLK 40
+#define GK7202V300_UART1_CLK 41
+#define GK7202V300_UART2_CLK 42
+#define GK7202V300_FMC_CLK 43
+#define GK7202V300_ETH0_CLK 44
+#define GK7202V300_EDMAC_AXICLK 45
+#define GK7202V300_EDMAC_CLK 46
+#define GK7202V300_SPI0_CLK 48
+#define GK7202V300_SPI1_CLK 49
+#define GK7202V300_MMC0_CLK 50
+#define GK7202V300_MMC1_CLK 51
+#define GK7202V300_MMC2_CLK 52
+#define GK7202V300_I2C0_CLK 53
+#define GK7202V300_I2C1_CLK 54
+#define GK7202V300_I2C2_CLK 55
+#define GK7202V300_USB2_BUS_CLK 81
+#define GK7202V300_USB2_REF_CLK 82
+#define GK7202V300_USB2_UTMI_CLK 83
+#define GK7202V300_USB2_PHY_APB_CLK 84
+#define GK7202V300_USB2_PHY_PLL_CLK 85
+#define GK7202V300_USB2_PHY_XO_CLK 86
+
+#define GK7202V300_NR_CLKS 256
+#define GK7202V300_NR_RSTS 256
+
+#endif /* __DTS_GK7202V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-metag-boot-dts-include-dt-bindings-clock-gk7205v200-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V200_CLOCK_H
+#define __DTS_GK7205V200_CLOCK_H
+
+/* clk in GK7205V200 CRG */
+/* fixed rate clocks */
+#define GK7205V200_FIXED_100K 1
+#define GK7205V200_FIXED_400K 2
+#define GK7205V200_FIXED_3M 3
+#define GK7205V200_FIXED_6M 4
+#define GK7205V200_FIXED_12M 5
+#define GK7205V200_FIXED_24M 6
+#define GK7205V200_FIXED_25M 7
+#define GK7205V200_FIXED_50M 8
+#define GK7205V200_FIXED_83P3M 9
+#define GK7205V200_FIXED_90M 10
+#define GK7205V200_FIXED_100M 11
+#define GK7205V200_FIXED_112M 12
+#define GK7205V200_FIXED_125M 13
+#define GK7205V200_FIXED_148P5M 14
+#define GK7205V200_FIXED_150M 15
+#define GK7205V200_FIXED_200M 16
+#define GK7205V200_FIXED_250M 17
+#define GK7205V200_FIXED_300M 18
+#define GK7205V200_FIXED_324M 19
+#define GK7205V200_FIXED_342M 20
+#define GK7205V200_FIXED_375M 21
+#define GK7205V200_FIXED_400M 22
+#define GK7205V200_FIXED_448M 23
+#define GK7205V200_FIXED_500M 24
+#define GK7205V200_FIXED_540M 25
+#define GK7205V200_FIXED_600M 26
+#define GK7205V200_FIXED_750M 27
+#define GK7205V200_FIXED_1000M 28
+#define GK7205V200_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V200_SYSAXI_CLK 30
+#define GK7205V200_SYSAPB_CLK 31
+#define GK7205V200_FMC_MUX 32
+#define GK7205V200_UART_MUX 33
+#define GK7205V200_MMC0_MUX 34
+#define GK7205V200_MMC1_MUX 35
+#define GK7205V200_MMC2_MUX 36
+#define GK7205V200_ETH_MUX 37
+#define GK7205V200_USB2_MUX 80
+/* gate clocks */
+#define GK7205V200_UART0_CLK 40
+#define GK7205V200_UART1_CLK 41
+#define GK7205V200_UART2_CLK 42
+#define GK7205V200_FMC_CLK 43
+#define GK7205V200_ETH0_CLK 44
+#define GK7205V200_EDMAC_AXICLK 45
+#define GK7205V200_EDMAC_CLK 46
+#define GK7205V200_SPI0_CLK 48
+#define GK7205V200_SPI1_CLK 49
+#define GK7205V200_MMC0_CLK 50
+#define GK7205V200_MMC1_CLK 51
+#define GK7205V200_MMC2_CLK 52
+#define GK7205V200_I2C0_CLK 53
+#define GK7205V200_I2C1_CLK 54
+#define GK7205V200_I2C2_CLK 55
+#define GK7205V200_USB2_BUS_CLK 81
+#define GK7205V200_USB2_REF_CLK 82
+#define GK7205V200_USB2_UTMI_CLK 83
+#define GK7205V200_USB2_PHY_APB_CLK 84
+#define GK7205V200_USB2_PHY_PLL_CLK 85
+#define GK7205V200_USB2_PHY_XO_CLK 86
+
+#define GK7205V200_NR_CLKS 256
+#define GK7205V200_NR_RSTS 256
+
+#endif /* __DTS_GK7205V200_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-metag-boot-dts-include-dt-bindings-clock-gk7205v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V300_CLOCK_H
+#define __DTS_GK7205V300_CLOCK_H
+
+/* clk in GK7205V300 CRG */
+/* fixed rate clocks */
+#define GK7205V300_FIXED_100K 1
+#define GK7205V300_FIXED_400K 2
+#define GK7205V300_FIXED_3M 3
+#define GK7205V300_FIXED_6M 4
+#define GK7205V300_FIXED_12M 5
+#define GK7205V300_FIXED_24M 6
+#define GK7205V300_FIXED_25M 7
+#define GK7205V300_FIXED_50M 8
+#define GK7205V300_FIXED_83P3M 9
+#define GK7205V300_FIXED_90M 10
+#define GK7205V300_FIXED_100M 11
+#define GK7205V300_FIXED_112M 12
+#define GK7205V300_FIXED_125M 13
+#define GK7205V300_FIXED_148P5M 14
+#define GK7205V300_FIXED_150M 15
+#define GK7205V300_FIXED_200M 16
+#define GK7205V300_FIXED_250M 17
+#define GK7205V300_FIXED_300M 18
+#define GK7205V300_FIXED_324M 19
+#define GK7205V300_FIXED_342M 20
+#define GK7205V300_FIXED_375M 21
+#define GK7205V300_FIXED_400M 22
+#define GK7205V300_FIXED_448M 23
+#define GK7205V300_FIXED_500M 24
+#define GK7205V300_FIXED_540M 25
+#define GK7205V300_FIXED_600M 26
+#define GK7205V300_FIXED_750M 27
+#define GK7205V300_FIXED_1000M 28
+#define GK7205V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V300_SYSAXI_CLK 30
+#define GK7205V300_SYSAPB_CLK 31
+#define GK7205V300_FMC_MUX 32
+#define GK7205V300_UART_MUX 33
+#define GK7205V300_MMC0_MUX 34
+#define GK7205V300_MMC1_MUX 35
+#define GK7205V300_MMC2_MUX 36
+#define GK7205V300_ETH_MUX 37
+#define GK7205V300_USB2_MUX 80
+/* gate clocks */
+#define GK7205V300_UART0_CLK 40
+#define GK7205V300_UART1_CLK 41
+#define GK7205V300_UART2_CLK 42
+#define GK7205V300_FMC_CLK 43
+#define GK7205V300_ETH0_CLK 44
+#define GK7205V300_EDMAC_AXICLK 45
+#define GK7205V300_EDMAC_CLK 46
+#define GK7205V300_SPI0_CLK 48
+#define GK7205V300_SPI1_CLK 49
+#define GK7205V300_MMC0_CLK 50
+#define GK7205V300_MMC1_CLK 51
+#define GK7205V300_MMC2_CLK 52
+#define GK7205V300_I2C0_CLK 53
+#define GK7205V300_I2C1_CLK 54
+#define GK7205V300_I2C2_CLK 55
+#define GK7205V300_USB2_BUS_CLK 81
+#define GK7205V300_USB2_REF_CLK 82
+#define GK7205V300_USB2_UTMI_CLK 83
+#define GK7205V300_USB2_PHY_APB_CLK 84
+#define GK7205V300_USB2_PHY_PLL_CLK 85
+#define GK7205V300_USB2_PHY_XO_CLK 86
+
+#define GK7205V300_NR_CLKS 256
+#define GK7205V300_NR_RSTS 256
+
+#endif /* __DTS_GK7205V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-metag-boot-dts-include-dt-bindings-clock-gk7605v100-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/metag/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/metag/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7605V100_CLOCK_H
+#define __DTS_GK7605V100_CLOCK_H
+
+/* clk in GK7605V100 CRG */
+/* fixed rate clocks */
+#define GK7605V100_FIXED_100K 1
+#define GK7605V100_FIXED_400K 2
+#define GK7605V100_FIXED_3M 3
+#define GK7605V100_FIXED_6M 4
+#define GK7605V100_FIXED_12M 5
+#define GK7605V100_FIXED_24M 6
+#define GK7605V100_FIXED_25M 7
+#define GK7605V100_FIXED_50M 8
+#define GK7605V100_FIXED_83P3M 9
+#define GK7605V100_FIXED_90M 10
+#define GK7605V100_FIXED_100M 11
+#define GK7605V100_FIXED_112M 12
+#define GK7605V100_FIXED_125M 13
+#define GK7605V100_FIXED_148P5M 14
+#define GK7605V100_FIXED_150M 15
+#define GK7605V100_FIXED_200M 16
+#define GK7605V100_FIXED_250M 17
+#define GK7605V100_FIXED_300M 18
+#define GK7605V100_FIXED_324M 19
+#define GK7605V100_FIXED_342M 20
+#define GK7605V100_FIXED_375M 21
+#define GK7605V100_FIXED_400M 22
+#define GK7605V100_FIXED_448M 23
+#define GK7605V100_FIXED_500M 24
+#define GK7605V100_FIXED_540M 25
+#define GK7605V100_FIXED_600M 26
+#define GK7605V100_FIXED_750M 27
+#define GK7605V100_FIXED_1000M 28
+#define GK7605V100_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7605V100_SYSAXI_CLK 30
+#define GK7605V100_SYSAPB_CLK 31
+#define GK7605V100_FMC_MUX 32
+#define GK7605V100_UART_MUX 33
+#define GK7605V100_MMC0_MUX 34
+#define GK7605V100_MMC1_MUX 35
+#define GK7605V100_MMC2_MUX 36
+#define GK7605V100_ETH_MUX 37
+#define GK7605V100_USB2_MUX 80
+/* gate clocks */
+#define GK7605V100_UART0_CLK 40
+#define GK7605V100_UART1_CLK 41
+#define GK7605V100_UART2_CLK 42
+#define GK7605V100_FMC_CLK 43
+#define GK7605V100_ETH0_CLK 44
+#define GK7605V100_EDMAC_AXICLK 45
+#define GK7605V100_EDMAC_CLK 46
+#define GK7605V100_SPI0_CLK 48
+#define GK7605V100_SPI1_CLK 49
+#define GK7605V100_MMC0_CLK 50
+#define GK7605V100_MMC1_CLK 51
+#define GK7605V100_MMC2_CLK 52
+#define GK7605V100_I2C0_CLK 53
+#define GK7605V100_I2C1_CLK 54
+#define GK7605V100_I2C2_CLK 55
+#define GK7605V100_USB2_BUS_CLK 81
+#define GK7605V100_USB2_REF_CLK 82
+#define GK7605V100_USB2_UTMI_CLK 83
+#define GK7605V100_USB2_PHY_APB_CLK 84
+#define GK7605V100_USB2_PHY_PLL_CLK 85
+#define GK7605V100_USB2_PHY_XO_CLK 86
+
+#define GK7605V100_NR_CLKS 256
+#define GK7605V100_NR_RSTS 256
+
+#endif /* __DTS_GK7605V100_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-mips-boot-dts-include-dt-bindings-clock-gk7202v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7202V300_CLOCK_H
+#define __DTS_GK7202V300_CLOCK_H
+
+/* clk in GK7202V300 CRG */
+/* fixed rate clocks */
+#define GK7202V300_FIXED_100K 1
+#define GK7202V300_FIXED_400K 2
+#define GK7202V300_FIXED_3M 3
+#define GK7202V300_FIXED_6M 4
+#define GK7202V300_FIXED_12M 5
+#define GK7202V300_FIXED_24M 6
+#define GK7202V300_FIXED_25M 7
+#define GK7202V300_FIXED_50M 8
+#define GK7202V300_FIXED_83P3M 9
+#define GK7202V300_FIXED_90M 10
+#define GK7202V300_FIXED_100M 11
+#define GK7202V300_FIXED_112M 12
+#define GK7202V300_FIXED_125M 13
+#define GK7202V300_FIXED_148P5M 14
+#define GK7202V300_FIXED_150M 15
+#define GK7202V300_FIXED_200M 16
+#define GK7202V300_FIXED_250M 17
+#define GK7202V300_FIXED_300M 18
+#define GK7202V300_FIXED_324M 19
+#define GK7202V300_FIXED_342M 20
+#define GK7202V300_FIXED_375M 21
+#define GK7202V300_FIXED_400M 22
+#define GK7202V300_FIXED_448M 23
+#define GK7202V300_FIXED_500M 24
+#define GK7202V300_FIXED_540M 25
+#define GK7202V300_FIXED_600M 26
+#define GK7202V300_FIXED_750M 27
+#define GK7202V300_FIXED_1000M 28
+#define GK7202V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7202V300_SYSAXI_CLK 30
+#define GK7202V300_SYSAPB_CLK 31
+#define GK7202V300_FMC_MUX 32
+#define GK7202V300_UART_MUX 33
+#define GK7202V300_MMC0_MUX 34
+#define GK7202V300_MMC1_MUX 35
+#define GK7202V300_MMC2_MUX 36
+#define GK7202V300_ETH_MUX 37
+#define GK7202V300_USB2_MUX 80
+/* gate clocks */
+#define GK7202V300_UART0_CLK 40
+#define GK7202V300_UART1_CLK 41
+#define GK7202V300_UART2_CLK 42
+#define GK7202V300_FMC_CLK 43
+#define GK7202V300_ETH0_CLK 44
+#define GK7202V300_EDMAC_AXICLK 45
+#define GK7202V300_EDMAC_CLK 46
+#define GK7202V300_SPI0_CLK 48
+#define GK7202V300_SPI1_CLK 49
+#define GK7202V300_MMC0_CLK 50
+#define GK7202V300_MMC1_CLK 51
+#define GK7202V300_MMC2_CLK 52
+#define GK7202V300_I2C0_CLK 53
+#define GK7202V300_I2C1_CLK 54
+#define GK7202V300_I2C2_CLK 55
+#define GK7202V300_USB2_BUS_CLK 81
+#define GK7202V300_USB2_REF_CLK 82
+#define GK7202V300_USB2_UTMI_CLK 83
+#define GK7202V300_USB2_PHY_APB_CLK 84
+#define GK7202V300_USB2_PHY_PLL_CLK 85
+#define GK7202V300_USB2_PHY_XO_CLK 86
+
+#define GK7202V300_NR_CLKS 256
+#define GK7202V300_NR_RSTS 256
+
+#endif /* __DTS_GK7202V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-mips-boot-dts-include-dt-bindings-clock-gk7205v200-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V200_CLOCK_H
+#define __DTS_GK7205V200_CLOCK_H
+
+/* clk in GK7205V200 CRG */
+/* fixed rate clocks */
+#define GK7205V200_FIXED_100K 1
+#define GK7205V200_FIXED_400K 2
+#define GK7205V200_FIXED_3M 3
+#define GK7205V200_FIXED_6M 4
+#define GK7205V200_FIXED_12M 5
+#define GK7205V200_FIXED_24M 6
+#define GK7205V200_FIXED_25M 7
+#define GK7205V200_FIXED_50M 8
+#define GK7205V200_FIXED_83P3M 9
+#define GK7205V200_FIXED_90M 10
+#define GK7205V200_FIXED_100M 11
+#define GK7205V200_FIXED_112M 12
+#define GK7205V200_FIXED_125M 13
+#define GK7205V200_FIXED_148P5M 14
+#define GK7205V200_FIXED_150M 15
+#define GK7205V200_FIXED_200M 16
+#define GK7205V200_FIXED_250M 17
+#define GK7205V200_FIXED_300M 18
+#define GK7205V200_FIXED_324M 19
+#define GK7205V200_FIXED_342M 20
+#define GK7205V200_FIXED_375M 21
+#define GK7205V200_FIXED_400M 22
+#define GK7205V200_FIXED_448M 23
+#define GK7205V200_FIXED_500M 24
+#define GK7205V200_FIXED_540M 25
+#define GK7205V200_FIXED_600M 26
+#define GK7205V200_FIXED_750M 27
+#define GK7205V200_FIXED_1000M 28
+#define GK7205V200_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V200_SYSAXI_CLK 30
+#define GK7205V200_SYSAPB_CLK 31
+#define GK7205V200_FMC_MUX 32
+#define GK7205V200_UART_MUX 33
+#define GK7205V200_MMC0_MUX 34
+#define GK7205V200_MMC1_MUX 35
+#define GK7205V200_MMC2_MUX 36
+#define GK7205V200_ETH_MUX 37
+#define GK7205V200_USB2_MUX 80
+/* gate clocks */
+#define GK7205V200_UART0_CLK 40
+#define GK7205V200_UART1_CLK 41
+#define GK7205V200_UART2_CLK 42
+#define GK7205V200_FMC_CLK 43
+#define GK7205V200_ETH0_CLK 44
+#define GK7205V200_EDMAC_AXICLK 45
+#define GK7205V200_EDMAC_CLK 46
+#define GK7205V200_SPI0_CLK 48
+#define GK7205V200_SPI1_CLK 49
+#define GK7205V200_MMC0_CLK 50
+#define GK7205V200_MMC1_CLK 51
+#define GK7205V200_MMC2_CLK 52
+#define GK7205V200_I2C0_CLK 53
+#define GK7205V200_I2C1_CLK 54
+#define GK7205V200_I2C2_CLK 55
+#define GK7205V200_USB2_BUS_CLK 81
+#define GK7205V200_USB2_REF_CLK 82
+#define GK7205V200_USB2_UTMI_CLK 83
+#define GK7205V200_USB2_PHY_APB_CLK 84
+#define GK7205V200_USB2_PHY_PLL_CLK 85
+#define GK7205V200_USB2_PHY_XO_CLK 86
+
+#define GK7205V200_NR_CLKS 256
+#define GK7205V200_NR_RSTS 256
+
+#endif /* __DTS_GK7205V200_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-mips-boot-dts-include-dt-bindings-clock-gk7205v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V300_CLOCK_H
+#define __DTS_GK7205V300_CLOCK_H
+
+/* clk in GK7205V300 CRG */
+/* fixed rate clocks */
+#define GK7205V300_FIXED_100K 1
+#define GK7205V300_FIXED_400K 2
+#define GK7205V300_FIXED_3M 3
+#define GK7205V300_FIXED_6M 4
+#define GK7205V300_FIXED_12M 5
+#define GK7205V300_FIXED_24M 6
+#define GK7205V300_FIXED_25M 7
+#define GK7205V300_FIXED_50M 8
+#define GK7205V300_FIXED_83P3M 9
+#define GK7205V300_FIXED_90M 10
+#define GK7205V300_FIXED_100M 11
+#define GK7205V300_FIXED_112M 12
+#define GK7205V300_FIXED_125M 13
+#define GK7205V300_FIXED_148P5M 14
+#define GK7205V300_FIXED_150M 15
+#define GK7205V300_FIXED_200M 16
+#define GK7205V300_FIXED_250M 17
+#define GK7205V300_FIXED_300M 18
+#define GK7205V300_FIXED_324M 19
+#define GK7205V300_FIXED_342M 20
+#define GK7205V300_FIXED_375M 21
+#define GK7205V300_FIXED_400M 22
+#define GK7205V300_FIXED_448M 23
+#define GK7205V300_FIXED_500M 24
+#define GK7205V300_FIXED_540M 25
+#define GK7205V300_FIXED_600M 26
+#define GK7205V300_FIXED_750M 27
+#define GK7205V300_FIXED_1000M 28
+#define GK7205V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V300_SYSAXI_CLK 30
+#define GK7205V300_SYSAPB_CLK 31
+#define GK7205V300_FMC_MUX 32
+#define GK7205V300_UART_MUX 33
+#define GK7205V300_MMC0_MUX 34
+#define GK7205V300_MMC1_MUX 35
+#define GK7205V300_MMC2_MUX 36
+#define GK7205V300_ETH_MUX 37
+#define GK7205V300_USB2_MUX 80
+/* gate clocks */
+#define GK7205V300_UART0_CLK 40
+#define GK7205V300_UART1_CLK 41
+#define GK7205V300_UART2_CLK 42
+#define GK7205V300_FMC_CLK 43
+#define GK7205V300_ETH0_CLK 44
+#define GK7205V300_EDMAC_AXICLK 45
+#define GK7205V300_EDMAC_CLK 46
+#define GK7205V300_SPI0_CLK 48
+#define GK7205V300_SPI1_CLK 49
+#define GK7205V300_MMC0_CLK 50
+#define GK7205V300_MMC1_CLK 51
+#define GK7205V300_MMC2_CLK 52
+#define GK7205V300_I2C0_CLK 53
+#define GK7205V300_I2C1_CLK 54
+#define GK7205V300_I2C2_CLK 55
+#define GK7205V300_USB2_BUS_CLK 81
+#define GK7205V300_USB2_REF_CLK 82
+#define GK7205V300_USB2_UTMI_CLK 83
+#define GK7205V300_USB2_PHY_APB_CLK 84
+#define GK7205V300_USB2_PHY_PLL_CLK 85
+#define GK7205V300_USB2_PHY_XO_CLK 86
+
+#define GK7205V300_NR_CLKS 256
+#define GK7205V300_NR_RSTS 256
+
+#endif /* __DTS_GK7205V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-mips-boot-dts-include-dt-bindings-clock-gk7605v100-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/mips/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/mips/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7605V100_CLOCK_H
+#define __DTS_GK7605V100_CLOCK_H
+
+/* clk in GK7605V100 CRG */
+/* fixed rate clocks */
+#define GK7605V100_FIXED_100K 1
+#define GK7605V100_FIXED_400K 2
+#define GK7605V100_FIXED_3M 3
+#define GK7605V100_FIXED_6M 4
+#define GK7605V100_FIXED_12M 5
+#define GK7605V100_FIXED_24M 6
+#define GK7605V100_FIXED_25M 7
+#define GK7605V100_FIXED_50M 8
+#define GK7605V100_FIXED_83P3M 9
+#define GK7605V100_FIXED_90M 10
+#define GK7605V100_FIXED_100M 11
+#define GK7605V100_FIXED_112M 12
+#define GK7605V100_FIXED_125M 13
+#define GK7605V100_FIXED_148P5M 14
+#define GK7605V100_FIXED_150M 15
+#define GK7605V100_FIXED_200M 16
+#define GK7605V100_FIXED_250M 17
+#define GK7605V100_FIXED_300M 18
+#define GK7605V100_FIXED_324M 19
+#define GK7605V100_FIXED_342M 20
+#define GK7605V100_FIXED_375M 21
+#define GK7605V100_FIXED_400M 22
+#define GK7605V100_FIXED_448M 23
+#define GK7605V100_FIXED_500M 24
+#define GK7605V100_FIXED_540M 25
+#define GK7605V100_FIXED_600M 26
+#define GK7605V100_FIXED_750M 27
+#define GK7605V100_FIXED_1000M 28
+#define GK7605V100_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7605V100_SYSAXI_CLK 30
+#define GK7605V100_SYSAPB_CLK 31
+#define GK7605V100_FMC_MUX 32
+#define GK7605V100_UART_MUX 33
+#define GK7605V100_MMC0_MUX 34
+#define GK7605V100_MMC1_MUX 35
+#define GK7605V100_MMC2_MUX 36
+#define GK7605V100_ETH_MUX 37
+#define GK7605V100_USB2_MUX 80
+/* gate clocks */
+#define GK7605V100_UART0_CLK 40
+#define GK7605V100_UART1_CLK 41
+#define GK7605V100_UART2_CLK 42
+#define GK7605V100_FMC_CLK 43
+#define GK7605V100_ETH0_CLK 44
+#define GK7605V100_EDMAC_AXICLK 45
+#define GK7605V100_EDMAC_CLK 46
+#define GK7605V100_SPI0_CLK 48
+#define GK7605V100_SPI1_CLK 49
+#define GK7605V100_MMC0_CLK 50
+#define GK7605V100_MMC1_CLK 51
+#define GK7605V100_MMC2_CLK 52
+#define GK7605V100_I2C0_CLK 53
+#define GK7605V100_I2C1_CLK 54
+#define GK7605V100_I2C2_CLK 55
+#define GK7605V100_USB2_BUS_CLK 81
+#define GK7605V100_USB2_REF_CLK 82
+#define GK7605V100_USB2_UTMI_CLK 83
+#define GK7605V100_USB2_PHY_APB_CLK 84
+#define GK7605V100_USB2_PHY_PLL_CLK 85
+#define GK7605V100_USB2_PHY_XO_CLK 86
+
+#define GK7605V100_NR_CLKS 256
+#define GK7605V100_NR_RSTS 256
+
+#endif /* __DTS_GK7605V100_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-powerpc-boot-dts-include-dt-bindings-clock-gk7202v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7202v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7202V300_CLOCK_H
+#define __DTS_GK7202V300_CLOCK_H
+
+/* clk in GK7202V300 CRG */
+/* fixed rate clocks */
+#define GK7202V300_FIXED_100K 1
+#define GK7202V300_FIXED_400K 2
+#define GK7202V300_FIXED_3M 3
+#define GK7202V300_FIXED_6M 4
+#define GK7202V300_FIXED_12M 5
+#define GK7202V300_FIXED_24M 6
+#define GK7202V300_FIXED_25M 7
+#define GK7202V300_FIXED_50M 8
+#define GK7202V300_FIXED_83P3M 9
+#define GK7202V300_FIXED_90M 10
+#define GK7202V300_FIXED_100M 11
+#define GK7202V300_FIXED_112M 12
+#define GK7202V300_FIXED_125M 13
+#define GK7202V300_FIXED_148P5M 14
+#define GK7202V300_FIXED_150M 15
+#define GK7202V300_FIXED_200M 16
+#define GK7202V300_FIXED_250M 17
+#define GK7202V300_FIXED_300M 18
+#define GK7202V300_FIXED_324M 19
+#define GK7202V300_FIXED_342M 20
+#define GK7202V300_FIXED_375M 21
+#define GK7202V300_FIXED_400M 22
+#define GK7202V300_FIXED_448M 23
+#define GK7202V300_FIXED_500M 24
+#define GK7202V300_FIXED_540M 25
+#define GK7202V300_FIXED_600M 26
+#define GK7202V300_FIXED_750M 27
+#define GK7202V300_FIXED_1000M 28
+#define GK7202V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7202V300_SYSAXI_CLK 30
+#define GK7202V300_SYSAPB_CLK 31
+#define GK7202V300_FMC_MUX 32
+#define GK7202V300_UART_MUX 33
+#define GK7202V300_MMC0_MUX 34
+#define GK7202V300_MMC1_MUX 35
+#define GK7202V300_MMC2_MUX 36
+#define GK7202V300_ETH_MUX 37
+#define GK7202V300_USB2_MUX 80
+/* gate clocks */
+#define GK7202V300_UART0_CLK 40
+#define GK7202V300_UART1_CLK 41
+#define GK7202V300_UART2_CLK 42
+#define GK7202V300_FMC_CLK 43
+#define GK7202V300_ETH0_CLK 44
+#define GK7202V300_EDMAC_AXICLK 45
+#define GK7202V300_EDMAC_CLK 46
+#define GK7202V300_SPI0_CLK 48
+#define GK7202V300_SPI1_CLK 49
+#define GK7202V300_MMC0_CLK 50
+#define GK7202V300_MMC1_CLK 51
+#define GK7202V300_MMC2_CLK 52
+#define GK7202V300_I2C0_CLK 53
+#define GK7202V300_I2C1_CLK 54
+#define GK7202V300_I2C2_CLK 55
+#define GK7202V300_USB2_BUS_CLK 81
+#define GK7202V300_USB2_REF_CLK 82
+#define GK7202V300_USB2_UTMI_CLK 83
+#define GK7202V300_USB2_PHY_APB_CLK 84
+#define GK7202V300_USB2_PHY_PLL_CLK 85
+#define GK7202V300_USB2_PHY_XO_CLK 86
+
+#define GK7202V300_NR_CLKS 256
+#define GK7202V300_NR_RSTS 256
+
+#endif /* __DTS_GK7202V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-powerpc-boot-dts-include-dt-bindings-clock-gk7205v200-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v200-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V200_CLOCK_H
+#define __DTS_GK7205V200_CLOCK_H
+
+/* clk in GK7205V200 CRG */
+/* fixed rate clocks */
+#define GK7205V200_FIXED_100K 1
+#define GK7205V200_FIXED_400K 2
+#define GK7205V200_FIXED_3M 3
+#define GK7205V200_FIXED_6M 4
+#define GK7205V200_FIXED_12M 5
+#define GK7205V200_FIXED_24M 6
+#define GK7205V200_FIXED_25M 7
+#define GK7205V200_FIXED_50M 8
+#define GK7205V200_FIXED_83P3M 9
+#define GK7205V200_FIXED_90M 10
+#define GK7205V200_FIXED_100M 11
+#define GK7205V200_FIXED_112M 12
+#define GK7205V200_FIXED_125M 13
+#define GK7205V200_FIXED_148P5M 14
+#define GK7205V200_FIXED_150M 15
+#define GK7205V200_FIXED_200M 16
+#define GK7205V200_FIXED_250M 17
+#define GK7205V200_FIXED_300M 18
+#define GK7205V200_FIXED_324M 19
+#define GK7205V200_FIXED_342M 20
+#define GK7205V200_FIXED_375M 21
+#define GK7205V200_FIXED_400M 22
+#define GK7205V200_FIXED_448M 23
+#define GK7205V200_FIXED_500M 24
+#define GK7205V200_FIXED_540M 25
+#define GK7205V200_FIXED_600M 26
+#define GK7205V200_FIXED_750M 27
+#define GK7205V200_FIXED_1000M 28
+#define GK7205V200_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V200_SYSAXI_CLK 30
+#define GK7205V200_SYSAPB_CLK 31
+#define GK7205V200_FMC_MUX 32
+#define GK7205V200_UART_MUX 33
+#define GK7205V200_MMC0_MUX 34
+#define GK7205V200_MMC1_MUX 35
+#define GK7205V200_MMC2_MUX 36
+#define GK7205V200_ETH_MUX 37
+#define GK7205V200_USB2_MUX 80
+/* gate clocks */
+#define GK7205V200_UART0_CLK 40
+#define GK7205V200_UART1_CLK 41
+#define GK7205V200_UART2_CLK 42
+#define GK7205V200_FMC_CLK 43
+#define GK7205V200_ETH0_CLK 44
+#define GK7205V200_EDMAC_AXICLK 45
+#define GK7205V200_EDMAC_CLK 46
+#define GK7205V200_SPI0_CLK 48
+#define GK7205V200_SPI1_CLK 49
+#define GK7205V200_MMC0_CLK 50
+#define GK7205V200_MMC1_CLK 51
+#define GK7205V200_MMC2_CLK 52
+#define GK7205V200_I2C0_CLK 53
+#define GK7205V200_I2C1_CLK 54
+#define GK7205V200_I2C2_CLK 55
+#define GK7205V200_USB2_BUS_CLK 81
+#define GK7205V200_USB2_REF_CLK 82
+#define GK7205V200_USB2_UTMI_CLK 83
+#define GK7205V200_USB2_PHY_APB_CLK 84
+#define GK7205V200_USB2_PHY_PLL_CLK 85
+#define GK7205V200_USB2_PHY_XO_CLK 86
+
+#define GK7205V200_NR_CLKS 256
+#define GK7205V200_NR_RSTS 256
+
+#endif /* __DTS_GK7205V200_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-powerpc-boot-dts-include-dt-bindings-clock-gk7205v300-clock.h.patch
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@ -1,79 +0,0 @@
--- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7205v300-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7205V300_CLOCK_H
+#define __DTS_GK7205V300_CLOCK_H
+
+/* clk in GK7205V300 CRG */
+/* fixed rate clocks */
+#define GK7205V300_FIXED_100K 1
+#define GK7205V300_FIXED_400K 2
+#define GK7205V300_FIXED_3M 3
+#define GK7205V300_FIXED_6M 4
+#define GK7205V300_FIXED_12M 5
+#define GK7205V300_FIXED_24M 6
+#define GK7205V300_FIXED_25M 7
+#define GK7205V300_FIXED_50M 8
+#define GK7205V300_FIXED_83P3M 9
+#define GK7205V300_FIXED_90M 10
+#define GK7205V300_FIXED_100M 11
+#define GK7205V300_FIXED_112M 12
+#define GK7205V300_FIXED_125M 13
+#define GK7205V300_FIXED_148P5M 14
+#define GK7205V300_FIXED_150M 15
+#define GK7205V300_FIXED_200M 16
+#define GK7205V300_FIXED_250M 17
+#define GK7205V300_FIXED_300M 18
+#define GK7205V300_FIXED_324M 19
+#define GK7205V300_FIXED_342M 20
+#define GK7205V300_FIXED_375M 21
+#define GK7205V300_FIXED_400M 22
+#define GK7205V300_FIXED_448M 23
+#define GK7205V300_FIXED_500M 24
+#define GK7205V300_FIXED_540M 25
+#define GK7205V300_FIXED_600M 26
+#define GK7205V300_FIXED_750M 27
+#define GK7205V300_FIXED_1000M 28
+#define GK7205V300_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7205V300_SYSAXI_CLK 30
+#define GK7205V300_SYSAPB_CLK 31
+#define GK7205V300_FMC_MUX 32
+#define GK7205V300_UART_MUX 33
+#define GK7205V300_MMC0_MUX 34
+#define GK7205V300_MMC1_MUX 35
+#define GK7205V300_MMC2_MUX 36
+#define GK7205V300_ETH_MUX 37
+#define GK7205V300_USB2_MUX 80
+/* gate clocks */
+#define GK7205V300_UART0_CLK 40
+#define GK7205V300_UART1_CLK 41
+#define GK7205V300_UART2_CLK 42
+#define GK7205V300_FMC_CLK 43
+#define GK7205V300_ETH0_CLK 44
+#define GK7205V300_EDMAC_AXICLK 45
+#define GK7205V300_EDMAC_CLK 46
+#define GK7205V300_SPI0_CLK 48
+#define GK7205V300_SPI1_CLK 49
+#define GK7205V300_MMC0_CLK 50
+#define GK7205V300_MMC1_CLK 51
+#define GK7205V300_MMC2_CLK 52
+#define GK7205V300_I2C0_CLK 53
+#define GK7205V300_I2C1_CLK 54
+#define GK7205V300_I2C2_CLK 55
+#define GK7205V300_USB2_BUS_CLK 81
+#define GK7205V300_USB2_REF_CLK 82
+#define GK7205V300_USB2_UTMI_CLK 83
+#define GK7205V300_USB2_PHY_APB_CLK 84
+#define GK7205V300_USB2_PHY_PLL_CLK 85
+#define GK7205V300_USB2_PHY_XO_CLK 86
+
+#define GK7205V300_NR_CLKS 256
+#define GK7205V300_NR_RSTS 256
+
+#endif /* __DTS_GK7205V300_CLOCK_H */

79
br-ext-chip-goke/board/gk7205v200/kernel/patches/00_arch-powerpc-boot-dts-include-dt-bindings-clock-gk7605v100-clock.h.patch
View File

@ -1,79 +0,0 @@
--- linux-4.9.37/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 1970-01-01 03:00:00.000000000 +0300
+++ linux-4.9.y/arch/powerpc/boot/dts/include/dt-bindings/clock/gk7605v100-clock.h 2021-06-07 13:01:34.000000000 +0300
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
+ */
+
+#ifndef __DTS_GK7605V100_CLOCK_H
+#define __DTS_GK7605V100_CLOCK_H
+
+/* clk in GK7605V100 CRG */
+/* fixed rate clocks */
+#define GK7605V100_FIXED_100K 1
+#define GK7605V100_FIXED_400K 2
+#define GK7605V100_FIXED_3M 3
+#define GK7605V100_FIXED_6M 4
+#define GK7605V100_FIXED_12M 5
+#define GK7605V100_FIXED_24M 6
+#define GK7605V100_FIXED_25M 7
+#define GK7605V100_FIXED_50M 8
+#define GK7605V100_FIXED_83P3M 9
+#define GK7605V100_FIXED_90M 10
+#define GK7605V100_FIXED_100M 11
+#define GK7605V100_FIXED_112M 12
+#define GK7605V100_FIXED_125M 13
+#define GK7605V100_FIXED_148P5M 14
+#define GK7605V100_FIXED_150M 15
+#define GK7605V100_FIXED_200M 16
+#define GK7605V100_FIXED_250M 17
+#define GK7605V100_FIXED_300M 18
+#define GK7605V100_FIXED_324M 19
+#define GK7605V100_FIXED_342M 20
+#define GK7605V100_FIXED_375M 21
+#define GK7605V100_FIXED_400M 22
+#define GK7605V100_FIXED_448M 23
+#define GK7605V100_FIXED_500M 24
+#define GK7605V100_FIXED_540M 25
+#define GK7605V100_FIXED_600M 26
+#define GK7605V100_FIXED_750M 27
+#define GK7605V100_FIXED_1000M 28
+#define GK7605V100_FIXED_1500M 29
+
+/* mux clocks */
+#define GK7605V100_SYSAXI_CLK 30
+#define GK7605V100_SYSAPB_CLK 31
+#define GK7605V100_FMC_MUX 32
+#define GK7605V100_UART_MUX 33
+#define GK7605V100_MMC0_MUX 34
+#define GK7605V100_MMC1_MUX 35
+#define GK7605V100_MMC2_MUX 36
+#define GK7605V100_ETH_MUX 37
+#define GK7605V100_USB2_MUX 80
+/* gate clocks */
+#define GK7605V100_UART0_CLK 40
+#define GK7605V100_UART1_CLK 41
+#define GK7605V100_UART2_CLK 42
+#define GK7605V100_FMC_CLK 43
+#define GK7605V100_ETH0_CLK 44
+#define GK7605V100_EDMAC_AXICLK 45
+#define GK7605V100_EDMAC_CLK 46
+#define GK7605V100_SPI0_CLK 48
+#define GK7605V100_SPI1_CLK 49
+#define GK7605V100_MMC0_CLK 50
+#define GK7605V100_MMC1_CLK 51
+#define GK7605V100_MMC2_CLK 52
+#define GK7605V100_I2C0_CLK 53
+#define GK7605V100_I2C1_CLK 54
+#define GK7605V100_I2C2_CLK 55
+#define GK7605V100_USB2_BUS_CLK 81
+#define GK7605V100_USB2_REF_CLK 82
+#define GK7605V100_USB2_UTMI_CLK 83
+#define GK7605V100_USB2_PHY_APB_CLK 84
+#define GK7605V100_USB2_PHY_PLL_CLK 85
+#define GK7605V100_USB2_PHY_XO_CLK 86
+
+#define GK7605V100_NR_CLKS 256
+#define GK7605V100_NR_RSTS 256
+
+#endif /* __DTS_GK7605V100_CLOCK_H */