Fix init for Hi3519v101

general/package/hisilicon-osdrv-hi3519v101/files/script/load_hisilicon

@@ -2,7 +2,7 @@
 #
 # This is part of OpenIPC.org project | 2022.01.07
 #
-
+#set -x
 # SoC detect
 chipid=$(ipcinfo --chip_id)
 
@@ -18,7 +18,9 @@ os_mem_size=${os_mem_size:=32}
 # Sensor config
 # SNS_TYPE=$(awk -F '=' '$1=="sensor"{print $2}' RS=" " /proc/cmdline)
 SNS_TYPE0=$(fw_printenv -n sensor)
-SNS_TYPE0=${SNS_TYPE0:=ov4689}
+SNS_TYPE0=${SNS_TYPE0:=imx290}
+SNS_TYPE1="NULL"
+WORK_MODE="single_pipe"
 
 report_error() {
 	echo "******* Error: There's something wrong, please check! *****"
@@ -69,6 +71,10 @@ remove_audio() {
 }
 
 sysconfig() {
+	devmem 0x100503c4 32 0x7
+	devmem 0x100503c0 32 0x11011f
+	devmem 0x100503c4 32 0xc004
+	devmem 0x100503c0 32 0x110113
 	vicap_pin_mux() {
 		#sensor0 pinmux
 		devmem 0x1204017c 32 0x1 #SENSOR0_CLK
@@ -228,9 +234,8 @@ sysconfig() {
 		vicap1_pwrdn >/dev/null
 	fi
 
-	#clkcfg
 	clkcfg() {
-		devmem 0x120100e4 32 0x1fff0000 # I2C0-3/SSP0-3 unreset, ir,enable clk gate
+		devmem 0x120100e4 32 0x1ff70000 # I2C0-3/SSP0-3 unreset, ir,enable clk gate
 		devmem 0x1201003c 32 0x31000100 # MIPI VI ISP unreset
 		devmem 0x12010050 32 0x2        # VEDU0 unreset
 		devmem 0x12010058 32 0x2        # VPSS0 unreset
@@ -269,8 +274,6 @@ sysconfig() {
 
 		# pcie clk enable
 		devmem 0x120100b0 32 0x000001f0
-
-		echo "clock configure operation done!"
 	}
 	vi_vpss_online_config() {
 		# -------------vi vpss online open
@@ -378,7 +381,7 @@ insert_sns() {
 			devmem 0x12010040 32 0x14 # sensor0 clk_en, 24MHz
 			i2c0_pin_mux
 			;;
-		imx290 | imx385)
+		imx290)
 			tmp=0x18
 			# SDK config:     IVE:396M,  GDC:475M,  VGS:500M,  VEDU:600M,   VPSS:300M
 			#imx290:viu0:340M,isp0:214M, viu1:340M,isp1:214M
@@ -387,6 +390,19 @@ insert_sns() {
 			devmem 0x12010040 32 0x18 # sensor0 clk_en, 37.125MHz
 			i2c0_pin_mux
 			;;
+		imx385)
+			tmp=0x18
+			devmem 0x12010040 32 0x18
+			devmem 0x12040190 32 0x2
+			devmem 0x1204018c 32 0x2
+			devmem 0x1204099c 32 0x120
+			devmem 0x12040998 32 0x120
+			insmod hi_ssp_sony.ko
+			devmem 0x12040184 32 0x1
+			devmem 0x12040188 32 0x1
+			devmem 0x12040010 32 0x2
+			devmem 0x12040014 32 0x2
+			;;
 		ov4689)
 			tmp=0x14
 			# SDK config:     IVE:396M,  GDC:475M,  VGS:500M,  VEDU:600M,   VPSS:300M
@@ -557,6 +573,11 @@ insert_ko() {
 
 	devmem 0x12010044 32 0x4ff0
 	devmem 0x12010044 32 0x4
+	devmem 0x12040098 32 0x3
+  	devmem 0x120100DC 32 0x6
+
+	devmem 0x1204008C 32 0x1
+	devmem 0x12040094 32 0x1
 	echo "==== Your input Sensor0 type is $SNS_TYPE0 ===="
 	echo "==== Your input Sensor1 type is $SNS_TYPE1 ===="
 }
@@ -568,8 +589,8 @@ remove_ko() {
 	rmmod hi_pwm
 	rmmod hi_piris
 
-	#rmmod hi3519v101_photo
+	rmmod hi3519v101_photo
-	rmmod hi3519v101_ive
+	#rmmod hi3519v101_ive
 
 	rmmod hi3519v101_rc
 	rmmod hi3519v101_jpege

general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/os08a_i2c_8M.ini

@@ -0,0 +1,80 @@
+[sensor]
+Sensor_type=stSnsOs08a10Obj
+Mode=WDR_MODE_NONE
+DllFile=libsns_os08a10.so
+
+[mode]
+input_mode=INPUT_MODE_MIPI
+dev_attr=0
+
+[mipi]
+data_type=2
+lane_id=0|1|2|3|-1|-1|-1|-1|
+
+[isp_image]
+Isp_FrameRate=30
+Isp_Bayer=BAYER_BGGR
+
+[vi_dev]
+Input_mod=VI_MODE_MIPI
+Work_mod =0     ;VI_WORK_MODE_1Multiplex = 0
+                ;VI_WORK_MODE_2Multiplex,
+                ;VI_WORK_MODE_4Multiplex
+Combine_mode =0 ;Y/C composite or separation mode
+                ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
+                ;VI_COMBINE_SEPARATE,     /*Separate mode */
+Comp_mode    =0 ;Component mode (single-component or dual-component)
+                ;VI_COMP_MODE_SINGLE = 0, /*single component mode */
+                ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
+Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge)
+                ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
+                ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
+Mask_num     =2 ;Component mask
+Mask_0       =0xFFF00000
+Mask_1       =0x0
+Scan_mode    = 1;VI_SCAN_INTERLACED = 0
+                ;VI_SCAN_PROGRESSIVE,
+Data_seq     =3 ;data sequence (ONLY for YUV format)
+                ;----2th component U/V sequence in bt1120
+                ;    VI_INPUT_DATA_VUVU = 0,
+                ;    VI_INPUT_DATA_UVUV,
+                ;----input sequence for yuv
+                ;    VI_INPUT_DATA_UYVY = 0,
+                ;    VI_INPUT_DATA_VYUY,
+                ;    VI_INPUT_DATA_YUYV,
+                ;    VI_INPUT_DATA_YVYU
+
+Vsync   =1      ; vertical synchronization signal
+                ;VI_VSYNC_FIELD = 0,
+                ;VI_VSYNC_PULSE,
+VsyncNeg=1      ;Polarity of the vertical synchronization signal
+                ;VI_VSYNC_NEG_HIGH = 0,
+                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
+Hsync  =0       ;Attribute of the horizontal synchronization signal
+                ;VI_HSYNC_VALID_SINGNAL = 0,
+                ;VI_HSYNC_PULSE,
+HsyncNeg =0     ;Polarity of the horizontal synchronization signal
+                ;VI_HSYNC_NEG_HIGH = 0,
+                ;VI_HSYNC_NEG_LOW
+VsyncValid =1   ;Attribute of the valid vertical synchronization signal
+                ;VI_VSYNC_NORM_PULSE = 0,
+                ;VI_VSYNC_VALID_SINGAL,
+VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
+                ;VI_VSYNC_VALID_NEG_HIGH = 0,
+                ;VI_VSYNC_VALID_NEG_LOW
+Timingblank_HsyncHfb =0     ;Horizontal front blanking width
+Timingblank_HsyncAct =1280  ;Horizontal effetive width
+Timingblank_HsyncHbb =0     ;Horizontal back blanking width
+Timingblank_VsyncVfb =0     ;Vertical front blanking height
+Timingblank_VsyncVact =720  ;Vertical effetive width
+Timingblank_VsyncVbb=0      ;Vertical back blanking height
+Timingblank_VsyncVbfb =0    ;Even-field vertical front blanking height(interlace, invalid progressive)
+Timingblank_VsyncVbact=0    ;Even-field vertical effetive width(interlace, invalid progressive)
+Timingblank_VsyncVbbb =0    ;Even-field vertical back blanking height(interlace, invalid progressive)
+DataPath=1
+InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
+DataRev      =FALSE ;Data reverse. FALSE = 0; TRUE = 1
+DevRect_x=0
+DevRect_y=0
+DevRect_w=3840
+DevRect_h=2160

general/package/hisilicon-osdrv-hi3519v101/hisilicon-osdrv-hi3519v101.mk

@@ -57,7 +57,7 @@ define HISILICON_OSDRV_HI3519V101_INSTALL_TARGET_CMDS
 	$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_pwm.ko
 	$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_sensor_i2c.ko
 	$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_sensor_spi.ko
-	# $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_ssp_sony.ko
+	$(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_ssp_sony.ko
 	# $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/3.18.20/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3519v101/files/kmod/hi_user.ko
 
 	$(INSTALL) -m 755 -d $(TARGET_DIR)/usr/bin