mirror of https://github.com/OpenIPC/firmware.git
675 lines
25 KiB
C
675 lines
25 KiB
C
/******************************************************************************
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Copyright (C), 2015-2020, XM. Co., Ltd.
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******************************************************************************
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File Name : xm550_isp.h
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Version : Initial Draft
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Author : XM Isp software group
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Created : 2016/11/26
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Description : The common data type defination
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Function List :
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History :
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1.Date : 2016/11/24
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Author : Ganwencao
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Modification : creat
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******************************************************************************/
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#ifndef _XM550_REG_
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#define _XM550_REG_
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#define DDR_BASE_ADDR (0x80000000)
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#define ISP_BASE_ADDR 0x30000000
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//video_main
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#define VIDEOMAIN_RGBIR_SEL (0x300f000c)
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//pre_video
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//CH1
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#define VIDEOMODE_BASE_CH1 (ISP_BASE_ADDR+0x0)
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#define VIDEOMODE_DECODE_SEL_CH1 (VIDOEMODE_BASE_CH1+0x000)
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#define VIDEOMODE_SLA_MAT_SEL_CH1 (VIDOEMODE_BASE_CH1+0x004)
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#define VIDEOMODE_DEC_DATA_SEL_CH1 (VIDOEMODE_BASE_CH1+0x008)
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//CH2
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//#define VIDOEMODE_BASE_CH2 0x30001000
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#define VIDEOMODE_BASE_CH2 (ISP_BASE_ADDR+0x1000)
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#define VIDEO2MODE_DECODE_SEL_CH2 (VIDOEMODE_BASE_CH2+0x000)
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#define VIDEO2MODE_SLA_MAT_SEL_CH2 (VIDOEMODE_BASE_CH2+0x004)
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#define VIDEO2MODE_DEC_DATA_SEL_CH2 (VIDOEMODE_BASE_CH2+0x008)
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// DPC
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//#define SDPC_BASE 0x30003000
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#define SDPC_BASE (ISP_BASE_ADDR+0x3000)
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#define SDPC_CLK_SW (SDPC_BASE+0x000)
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#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
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#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
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#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
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// BlackLevel
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#define BLACKLEVEL_BASE (ISP_BASE_ADDR+0x4000)
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#define BLACKLEVEL_OFFSET_R_CH1 (BLACKLEVEL_BASE+0x000)
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#define BLACKLEVEL_OFFSET_G_CH1 (BLACKLEVEL_BASE+0x004)
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#define BLACKLEVEL_OFFSET_B_CH1 (BLACKLEVEL_BASE+0x008)
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#define BLACKLEVEL_RGB_MAX_CH1 (BLACKLEVEL_BASE+0x00C)
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#define BLACKLEVEL_RGB_MIN_CH1 (BLACKLEVEL_BASE+0x010)
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#define BLACKLEVEL_OFFSET_R_CH2 (BLACKLEVEL_BASE+0x040)
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#define BLACKLEVEL_OFFSET_G_CH2 (BLACKLEVEL_BASE+0x044)
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#define BLACKLEVEL_OFFSET_B_CH2 (BLACKLEVEL_BASE+0x048)
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#define BLACKLEVEL_RGB_MAX_CH2 (BLACKLEVEL_BASE+0x04C)
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#define BLACKLEVEL_RGB_MIN_CH2 (BLACKLEVEL_BASE+0x050)
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// DIGTAL_GAIN
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#define DIGITAL_GAIN_BASE (ISP_BASE_ADDR+0x5000)
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#define DIGITAL_GAIN_CH1 (DIGITAL_GAIN_BASE+0x0)
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#define DIGITAL_GAIN_CH2 (DIGITAL_GAIN_BASE+0x10)
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//LSC
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#define LSC_BASE (ISP_BASE_ADDR+0x6000)
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#define LSC_CTRL (LSC_BASE+0x000)
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//HDR
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#define HDR_BASE (ISP_BASE_ADDR+0x0000)
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#define HDR_R_GAIN (HDR_BASE+0x8000)
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#define HDR_G_GAIN (HDR_BASE+0x8004)
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#define HDR_B_GAIN (HDR_BASE+0x8008)
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#define HDR_RGB_MAX (HDR_BASE+0x800C)
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#define HDR_RGB_MIN (HDR_BASE+0x8010)
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#define HDR_CLIP_WT_MAX (HDR_BASE+0x9000)
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#define HDR_CLIP_WT_MIN (HDR_BASE+0x9004)
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#define HDR_MOTION_THR (HDR_BASE+0x9008)
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#define HDR_V_MAX (HDR_BASE+0x900C)
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#define HDR_LS_TIME_RATIO (HDR_BASE+0x9010)
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#define HDR_LE_WT_MIN (HDR_BASE+0x9014)
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#define HDR_SE_WT_RATIO (HDR_BASE+0x9018)
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#define HDR_DCTTAB_DAT0 (HDR_BASE+0xA040)
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#define HDR_USMINTENS (HDR_BASE+0xB028)
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#define HDR_FUSWT (HDR_BASE+0xB02C)
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//NIR
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#define NIR_BASE (ISP_BASE_ADDR+0x30000)
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#define NIR_IR_INTG (NIR_BASE + 0x2000)
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#define NIR_R_INTG (NIR_BASE + 0x2004)
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#define NIR_G_INTG (NIR_BASE + 0x2008)
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#define NIR_B_INTG (NIR_BASE + 0x200C)
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#define NIR_RGB_INTG (NIR_BASE + 0x2010)
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#define NIR_RS_RAT (NIR_BASE + 0x1004)
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#define NIR_GS_RAT (NIR_BASE + 0x1008)
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#define NIR_BS_RAT (NIR_BASE + 0x100C)
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#define NIR_HIR_COEF1 (NIR_BASE + 0x0018)
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#define NIR_HIR_COEF2 (NIR_BASE + 0x001C)
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#define NIR_HIR_COEF3 (NIR_BASE + 0x0020)
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#define NIR_LUMLUT0 (NIR_BASE + 0x1080)
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//AWB
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#define AWB_BASE (ISP_BASE_ADDR+0x10000)
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#define AWB_FRONTGAIN_R_CH1 (AWB_BASE+0x0)
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#define AWB_FRONTGAIN_G_CH1 (AWB_BASE+0x4)
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#define AWB_FRONTGAIN_B_CH1 (AWB_BASE+0x8)
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#define AWB_RGBMAX_REG_CH1 (AWB_BASE+0xC)
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#define AWB_RGBMIN_REG_CH1 (AWB_BASE+0x10)
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#define AWB_FRONTGAIN_R_CH2 (AWB_BASE+0x40)
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#define AWB_FRONTGAIN_G_CH2 (AWB_BASE+0x44)
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#define AWB_FRONTGAIN_B_CH2 (AWB_BASE+0x48)
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#define AWB_RGBMAX_REG_CH2 (AWB_BASE+0x4C)
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#define AWB_RGBMIN_REG_CH2 (AWB_BASE+0x50)
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#define AWB_WDW_PIXL0 (AWB_BASE+0x1000)
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#define AWB_WDW_PIXL1 (AWB_BASE+0x1004)
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#define AWB_WDW_PIXL2 (AWB_BASE+0x1008)
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#define AWB_WDW_PIXL3 (AWB_BASE+0x100C)
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#define AWB_WDW_PIXL4 (AWB_BASE+0x1010)
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#define AWB_WDW_PIXL5 (AWB_BASE+0x1014)
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#define AWB_WDW_PIXL6 (AWB_BASE+0x1018)
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#define AWB_WDW_PIXL7 (AWB_BASE+0x101C)
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#define AWB_WDW_PIXL8 (AWB_BASE+0x1020)
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#define AWB_WDW_PIXL9 (AWB_BASE+0x1024)
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#define AWB_WDW_PIXL10 (AWB_BASE+0x1028)
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#define AWB_WDW_PIXL11 (AWB_BASE+0x102C)
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#define AWB_WDW_PIXL12 (AWB_BASE+0x1030)
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#define AWB_WDW_PIXL13 (AWB_BASE+0x1034)
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#define AWB_WDW_PIXL14 (AWB_BASE+0x1038)
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#define AWB_WDW_PIXL15 (AWB_BASE+0x103C)
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#define AWB_WDW_PIXL16 (AWB_BASE+0x1040)
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#define AWB_WDW_PIXL17 (AWB_BASE+0x1044)
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#define AWB_WDW_PIXL18 (AWB_BASE+0x1048)
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#define AWB_WDW_PIXL19 (AWB_BASE+0x104C)
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#define AWB_WDW_PIXL20 (AWB_BASE+0x1050)
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#define AWB_WDW_PIXL21 (AWB_BASE+0x1054)
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#define AWB_WDW_PIXL22 (AWB_BASE+0x1058)
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#define AWB_WDW_PIXL23 (AWB_BASE+0x105C)
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#define AWB_WDW_PIXL24 (AWB_BASE+0x1060)
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#define AWB_WDW_PIXL25 (AWB_BASE+0x1064)
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#define AWB_WDW_PIXL26 (AWB_BASE+0x1068)
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#define AWB_WDW_PIXL27 (AWB_BASE+0x106C)
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#define AWB_WDW_PIXL28 (AWB_BASE+0x1070)
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#define AWB_WDW_PIXL29 (AWB_BASE+0x1074)
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#define AWB_WDW_PIXL30 (AWB_BASE+0x1078)
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#define AWB_WDW_PIXL31 (AWB_BASE+0x107C)
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#define AWB_WDW_PIXL32 (AWB_BASE+0x1080)
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#define AWB_WDW_LINE0 (AWB_BASE+0x10C0)
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#define AWB_WDW_LINE1 (AWB_BASE+0x10C4)
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#define AWB_WDW_LINE2 (AWB_BASE+0x10C8)
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#define AWB_WDW_LINE3 (AWB_BASE+0x10CC)
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#define AWB_WDW_LINE4 (AWB_BASE+0x10D0)
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#define AWB_WDW_LINE5 (AWB_BASE+0x10D4)
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#define AWB_WDW_LINE6 (AWB_BASE+0x10D8)
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#define AWB_WDW_LINE7 (AWB_BASE+0x10DC)
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#define AWB_WDW_LINE8 (AWB_BASE+0x10E0)
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#define AWB_WDW_LINE9 (AWB_BASE+0x10E4)
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#define AWB_WDW_LINE10 (AWB_BASE+0x10E8)
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#define AWB_WDW_LINE11 (AWB_BASE+0x10EC)
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#define AWB_WDW_LINE12 (AWB_BASE+0x10F0)
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#define AWB_WDW_LINE13 (AWB_BASE+0x10F4)
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#define AWB_WDW_LINE14 (AWB_BASE+0x10F8)
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#define AWB_WDW_LINE15 (AWB_BASE+0x10FC)
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#define AWB_WDW_LINE16 (AWB_BASE+0x1100)
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#define AWB_SRAM_ADDR_RC (AWB_BASE+0x1140)
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#define AWB_SRAM_RD_EN (AWB_BASE+0x1144)
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#define AWB_R_INTG (AWB_BASE+0x1148)
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#define AWB_G_INTG (AWB_BASE+0x114C)
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#define AWB_B_INTG (AWB_BASE+0x1150)
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#define AWB_HDR_LS_MODE (AWB_BASE+0x1180)
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#define AWB_FRAME_CH_SEL (AWB_BASE+0x1184)
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#define AWB_HIST_RGB_SEL (AWB_BASE+0x2000)
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#define AWB_HIST_CNT0 (AWB_BASE+0x2040)
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#define AWB_HIST_CNT1 (AWB_BASE+0x2044)
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#define AWB_HIST_CNT2 (AWB_BASE+0x2048)
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#define AWB_HIST_CNT3 (AWB_BASE+0x204C)
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#define AWB_HIST_CNT4 (AWB_BASE+0x2050)
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#define AWB_HIST_CNT5 (AWB_BASE+0x2054)
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#define AWB_HIST_CNT6 (AWB_BASE+0x2058)
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#define AWB_HIST_CNT7 (AWB_BASE+0x205C)
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#define AWB_HIST_CNT8 (AWB_BASE+0x2060)
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#define AWB_HIST_CNT9 (AWB_BASE+0x2064)
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#define AWB_HIST_CNT10 (AWB_BASE+0x2068)
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#define AWB_HIST_CNT11 (AWB_BASE+0x206C)
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#define AWB_HIST_CNT12 (AWB_BASE+0x2070)
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#define AWB_HIST_CNT13 (AWB_BASE+0x2074)
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#define AWB_HIST_CNT14 (AWB_BASE+0x2078)
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#define AWB_HIST_CNT15 (AWB_BASE+0x207C)
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#define AWB_HIST_CNT16 (AWB_BASE+0x2080)
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#define AWB_HIST_CNT17 (AWB_BASE+0x2084)
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#define AWB_HIST_CNT18 (AWB_BASE+0x2088)
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#define AWB_HIST_CNT19 (AWB_BASE+0x208C)
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#define AWB_HIST_CNT20 (AWB_BASE+0x2090)
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#define AWB_HIST_CNT21 (AWB_BASE+0x2094)
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#define AWB_HIST_CNT22 (AWB_BASE+0x2098)
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#define AWB_HIST_CNT23 (AWB_BASE+0x209C)
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#define AWB_HIST_CNT24 (AWB_BASE+0x20A0)
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#define AWB_HIST_CNT25 (AWB_BASE+0x20A4)
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#define AWB_HIST_CNT26 (AWB_BASE+0x20A8)
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#define AWB_HIST_CNT27 (AWB_BASE+0x20AC)
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#define AWB_HIST_CNT28 (AWB_BASE+0x20B0)
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#define AWB_HIST_CNT29 (AWB_BASE+0x20B4)
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#define AWB_HIST_CNT30 (AWB_BASE+0x20B8)
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#define AWB_HIST_CNT31 (AWB_BASE+0x20BC)
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//AF
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#define DDPC_BASE (ISP_BASE_ADDR+0x23000)
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#define DDPC_MAX_THD (DDPC_BASE+0x000)
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#define DDPC_MIN_THD (DDPC_BASE+0x004)
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#define DDPC_DIFF_THD1 (DDPC_BASE+0x008)
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#define DDPC_DIFF_THD2 (DDPC_BASE+0x00C)
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//NR_2D
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#define NR_2D_BASE (ISP_BASE_ADDR+0x20000)
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#define NR_2D_THDL_REG_CH1 (NR_2D_BASE + 0x000)
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#define NR_2D_THDH_REG_CH1 (NR_2D_BASE + 0x004)
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#define NR_2D_COEF_REG_CH1 (NR_2D_BASE + 0x008)
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#define NR_2D_GMIN_REG_CH1 (NR_2D_BASE + 0x00C)
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#define NR_2D_DELTA_THD_CH1 (NR_2D_BASE + 0x010)
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#define NR_2D_G_COEF1_CH1 (NR_2D_BASE + 0x014)
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#define NR_2D_G_COEF2_CH1 (NR_2D_BASE + 0x018)
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#define NR_2D_G_COEF3_CH1 (NR_2D_BASE + 0x01C)
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#define NR_2D_G_COEF4_CH1 (NR_2D_BASE + 0x020)
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#define NR_2D_RB_COEF1_CH1 (NR_2D_BASE + 0x024)
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#define NR_2D_RB_COEF2_CH1 (NR_2D_BASE + 0x028)
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#define NR_2D_RB_COEF3_CH1 (NR_2D_BASE + 0x02C)
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#define NR_2D_H_SEL_CH1 (NR_2D_BASE + 0x030)
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#define NR_2D_FLT_EN_CH1 (NR_2D_BASE + 0x034)
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#define NR_2D_THDL_REG_CH2 (NR_2D_BASE + 0x040)
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#define NR_2D_THDH_REG_CH2 (NR_2D_BASE + 0x044)
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#define NR_2D_COEF_REG_CH2 (NR_2D_BASE + 0x048)
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#define NR_2D_GMIN_REG_CH2 (NR_2D_BASE + 0x04C)
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#define NR_2D_DELTA_THD_CH2 (NR_2D_BASE + 0x050)
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#define NR_2D_G_COEF1_CH2 (NR_2D_BASE + 0x054)
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#define NR_2D_G_COEF2_CH2 (NR_2D_BASE + 0x058)
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#define NR_2D_G_COEF3_CH2 (NR_2D_BASE + 0x05C)
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#define NR_2D_G_COEF4_CH2 (NR_2D_BASE + 0x060)
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#define NR_2D_RB_COEF1_CH2 (NR_2D_BASE + 0x064)
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#define NR_2D_RB_COEF2_CH2 (NR_2D_BASE + 0x068)
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#define NR_2D_RB_COEF3_CH2 (NR_2D_BASE + 0x06C)
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#define NR_2D_H_SEL_CH2 (NR_2D_BASE + 0x070)
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#define NR_2D_FLT_EN_CH2 (NR_2D_BASE + 0x074)
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//AF
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#define AF_BASE (ISP_BASE_ADDR+0x21000)
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#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
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#define AF_WDW0_VEND (AF_BASE + 0x004)
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#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
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#define AF_WDW0_HEND (AF_BASE + 0x00C)
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#define AF_WDW0_HZ (AF_BASE + 0x094)
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#if 1
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//NR_3D
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#define NR_3D_BASE_CH1 (ISP_BASE_ADDR+0x40000)
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#define NR_3D_DENOSIE_CTL_CH1 (NR_3D_BASE_CH1 + 0x000)
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#define NR_3D_RAMP_CH1 (NR_3D_BASE_CH1 + 0x004)
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#define NR_3D_G1AMP_CH1 (NR_3D_BASE_CH1 + 0x008)
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#define NR_3D_G2AMP_CH1 (NR_3D_BASE_CH1 + 0x00c)
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#define NR_3D_BAMP_CH1 (NR_3D_BASE_CH1 + 0x010)
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#define NR_3D_ERR_SFT_CH1 (NR_3D_BASE_CH1 + 0x014)
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#define NR_3D_DIG_E1_CH1 (NR_3D_BASE_CH1 + 0x020)
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#define NR_3D_DIG_E2_CH1 (NR_3D_BASE_CH1 + 0x024)
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#define NR_3D_DIG_E3_CH1 (NR_3D_BASE_CH1 + 0x028)
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#define NR_3D_DIG_E4_CH1 (NR_3D_BASE_CH1 + 0x02c)
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#define NR_3D_YFLD_SPACE_CH1 (NR_3D_BASE_CH1 + 0x030)
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#define NR_3D_BFLD_SPACE_CH1 (NR_3D_BASE_CH1 + 0x034)
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#define NR_3D_DFT_YSADDR0_CH1 (NR_3D_BASE_CH1 + 0x038)
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#define NR_3D_DFT_ESADDR0_CH1 (NR_3D_BASE_CH1 + 0x03C)
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#define NR_3D_ERR_PAR_CH1 (NR_3D_BASE_CH1 + 0x040)
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#define NR_3D_BAYER_PAR_CH1 (NR_3D_BASE_CH1 + 0x050)
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#define NR_3D_DFT_BSADDR0_CH1 (NR_3D_BASE_CH1 + 0x0A0)
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#define NR_3D_DFT_BSADDR1_CH1 (NR_3D_BASE_CH1 + 0x0A4)
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#define NR_3D_DFT_BSADDR2_CH1 (NR_3D_BASE_CH1 + 0x0A8)
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#define NR_3D_DFT_BSADDR3_CH1 (NR_3D_BASE_CH1 + 0x0AC)
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#define NR_3D_DFT_BSADDR4_CH1 (NR_3D_BASE_CH1 + 0x0B0)
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#define NR_3D_DFT_BSADDR5_CH1 (NR_3D_BASE_CH1 + 0x0B4)
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#define NR_3D_DFT_BSADDR6_CH1 (NR_3D_BASE_CH1 + 0x0B8)
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#define NR_3D_DFT_BSADDR7_CH1 (NR_3D_BASE_CH1 + 0x0BC)
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#define NR_3D_DDR_BHNUM_CH1 (NR_3D_BASE_CH1 + 0x0C8)
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#define NR_3D_DDR_YHNUM_CH1 (NR_3D_BASE_CH1 + 0x0CC)
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#define NR_3D_DDR_EHNUM_CH1 (NR_3D_BASE_CH1 + 0x0D0)
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#define NR_3D_ACTIVE_HNUM_CH1 (NR_3D_BASE_CH1 + 0x0D4)
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#define NR_3D_ACTIVE_VNUM_CH1 (NR_3D_BASE_CH1 + 0x0D8)
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#define NR_3D_WINERR_HBEGIN_CH1 (NR_3D_BASE_CH1 + 0x120)
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#define NR_3D_WINERR_HEND_CH1 (NR_3D_BASE_CH1 + 0x124)
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#define NR_3D_WINERR_VBEGIN_CH1 (NR_3D_BASE_CH1 + 0x128)
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#define NR_3D_WINERR_VEND_CH1 (NR_3D_BASE_CH1 + 0x12C)
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#define NR_3D_WINERR_RSHIFT_CH1 (NR_3D_BASE_CH1 + 0x140)
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#define NR_3D_WINERR_LEVEL_CH1 (NR_3D_BASE_CH1 + 0x144)
|
|
#define NR_3D_CHANGE_POINT_CH1 (NR_3D_BASE_CH1 + 0x148)
|
|
#define NR_3D_FLT2D_PAR_CH1 (NR_3D_BASE_CH1 + 0x14C)
|
|
|
|
|
|
#define NR_3D_BASE_CH2 (ISP_BASE_ADDR+0x40200)
|
|
#define NR_3D_DENOSIE_CTL_CH2 (NR_3D_BASE_CH2 + 0x000)
|
|
#define NR_3D_RAMP_CH2 (NR_3D_BASE_CH2 + 0x004)
|
|
#define NR_3D_G1AMP_CH2 (NR_3D_BASE_CH2 + 0x008)
|
|
#define NR_3D_G2AMP_CH2 (NR_3D_BASE_CH2 + 0x00c)
|
|
#define NR_3D_BAMP_CH2 (NR_3D_BASE_CH2 + 0x010)
|
|
#define NR_3D_ERR_SFT_CH2 (NR_3D_BASE_CH2 + 0x014)
|
|
|
|
#define NR_3D_DIG_E1_CH2 (NR_3D_BASE_CH2 + 0x020)
|
|
#define NR_3D_DIG_E2_CH2 (NR_3D_BASE_CH2 + 0x024)
|
|
#define NR_3D_DIG_E3_CH2 (NR_3D_BASE_CH2 + 0x028)
|
|
#define NR_3D_DIG_E4_CH2 (NR_3D_BASE_CH2 + 0x02c)
|
|
|
|
#define NR_3D_YFLD_SPACE_CH2 (NR_3D_BASE_CH2 + 0x030)
|
|
#define NR_3D_BFLD_SPACE_CH2 (NR_3D_BASE_CH2 + 0x034)
|
|
#define NR_3D_DFT_YSADDR0_CH2 (NR_3D_BASE_CH2 + 0x038)
|
|
#define NR_3D_DFT_ESADDR0_CH2 (NR_3D_BASE_CH2 + 0x03C)
|
|
|
|
#define NR_3D_ERR_PAR_CH2 (NR_3D_BASE_CH2 + 0x040)
|
|
#define NR_3D_BAYER_PAR_CH2 (NR_3D_BASE_CH2 + 0x050)
|
|
|
|
#define NR_3D_DFT_BSADDR0_CH2 (NR_3D_BASE_CH2 + 0x0A0)
|
|
#define NR_3D_DFT_BSADDR1_CH2 (NR_3D_BASE_CH2 + 0x0A4)
|
|
#define NR_3D_DFT_BSADDR2_CH2 (NR_3D_BASE_CH2 + 0x0A8)
|
|
#define NR_3D_DFT_BSADDR3_CH2 (NR_3D_BASE_CH2 + 0x0AC)
|
|
#define NR_3D_DFT_BSADDR4_CH2 (NR_3D_BASE_CH2 + 0x0B0)
|
|
#define NR_3D_DFT_BSADDR5_CH2 (NR_3D_BASE_CH2 + 0x0B4)
|
|
#define NR_3D_DFT_BSADDR6_CH2 (NR_3D_BASE_CH2 + 0x0B8)
|
|
#define NR_3D_DFT_BSADDR7_CH2 (NR_3D_BASE_CH2 + 0x0BC)
|
|
|
|
#define NR_3D_DDR_BHNUM_CH2 (NR_3D_BASE_CH2 + 0x0C8)
|
|
#define NR_3D_DDR_YHNUM_CH2 (NR_3D_BASE_CH2 + 0x0CC)
|
|
#define NR_3D_DDR_EHNUM_CH2 (NR_3D_BASE_CH2 + 0x0D0)
|
|
#define NR_3D_ACTIVE_HNUM_CH2 (NR_3D_BASE_CH2 + 0x0D4)
|
|
#define NR_3D_ACTIVE_VNUM_CH2 (NR_3D_BASE_CH2 + 0x0D8)
|
|
|
|
#define NR_3D_WINERR_HBEGIN_CH2 (NR_3D_BASE_CH2 + 0x120)
|
|
#define NR_3D_WINERR_HEND_CH2 (NR_3D_BASE_CH2 + 0x124)
|
|
#define NR_3D_WINERR_VBEGIN_CH2 (NR_3D_BASE_CH2 + 0x128)
|
|
#define NR_3D_WINERR_VEND_CH2 (NR_3D_BASE_CH2 + 0x12C)
|
|
|
|
#define NR_3D_WINERR_RSHIFT_CH2 (NR_3D_BASE_CH2 + 0x140)
|
|
#define NR_3D_WINERR_LEVEL_CH2 (NR_3D_BASE_CH2 + 0x144)
|
|
#define NR_3D_CHANGE_POINT_CH2 (NR_3D_BASE_CH2 + 0x148)
|
|
#define NR_3D_FLT2D_PAR_CH2 (NR_3D_BASE_CH2 + 0x14C)
|
|
#else// This is XM510 code,just for test
|
|
|
|
//NR_3D
|
|
#define NR_3D_BASE 0x30040000
|
|
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
|
|
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
|
|
#define NR_3D_NR_LEVEL (NR_3D_BASE + 0x018)
|
|
|
|
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
|
|
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
|
|
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
|
|
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
|
|
|
|
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
|
|
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
|
|
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
|
|
|
|
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
|
|
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
|
|
#define NR_3D_DDR_HNUM (NR_3D_BASE + 0x0D0)
|
|
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
|
|
#define NR_3D_YCTRL_ERR70 (NR_3D_BASE + 0x0D8)
|
|
#define NR_3D_YCTRL_ERRF8 (NR_3D_BASE + 0x0DC)
|
|
|
|
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
|
|
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
|
|
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
|
|
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
|
|
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
|
|
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
|
|
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
|
|
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
|
|
|
|
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
|
|
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
|
|
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
|
|
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
|
|
|
|
#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
|
|
#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
|
|
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
|
|
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
|
|
|
|
#endif
|
|
|
|
// Demosaic
|
|
#define DEMOSAIC_BASE (ISP_BASE_ADDR+0x52000)
|
|
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
|
|
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
|
|
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
|
|
|
|
// CSM
|
|
#define CSM_BASE (ISP_BASE_ADDR+0x60000)
|
|
|
|
#define CSM_RGB_MAX_CH1 (CSM_BASE+0x000)
|
|
#define CSM_RGB_MIN_CH1 (CSM_BASE+0x004)
|
|
|
|
#define CSM_R_OFST_REG_CH1 (CSM_BASE+0x040)
|
|
#define CSM_R1_COEF_REG_CH1 (CSM_BASE+0x044)
|
|
#define CSM_R2_COEF_REG_CH1 (CSM_BASE+0x048)
|
|
#define CSM_R3_COEF_REG_CH1 (CSM_BASE+0x04C)
|
|
#define CSM_G_OFST_REG_CH1 (CSM_BASE+0x050)
|
|
#define CSM_G1_COEF_REG_CH1 (CSM_BASE+0x054)
|
|
#define CSM_G2_COEF_REG_CH1 (CSM_BASE+0x058)
|
|
#define CSM_G3_COEF_REG_CH1 (CSM_BASE+0x05C)
|
|
#define CSM_B_OFST_REG_CH1 (CSM_BASE+0x060)
|
|
#define CSM_B1_COEF_REG_CH1 (CSM_BASE+0x064)
|
|
#define CSM_B2_COEF_REG_CH1 (CSM_BASE+0x068)
|
|
#define CSM_B3_COEF_REG_CH1 (CSM_BASE+0x06C)
|
|
|
|
#define CSM_RGB_MAX_CH2 (CSM_BASE+0x080)
|
|
#define CSM_RGB_MIN_CH2 (CSM_BASE+0x084)
|
|
|
|
#define CSM_R_OFST_REG_CH2 (CSM_BASE+0x0C0)
|
|
#define CSM_R1_COEF_REG_CH2 (CSM_BASE+0x0C4)
|
|
#define CSM_R2_COEF_REG_CH2 (CSM_BASE+0x0C8)
|
|
#define CSM_R3_COEF_REG_CH2 (CSM_BASE+0x0CC)
|
|
#define CSM_G_OFST_REG_CH2 (CSM_BASE+0x0D0)
|
|
#define CSM_G1_COEF_REG_CH2 (CSM_BASE+0x0D4)
|
|
#define CSM_G2_COEF_REG_CH2 (CSM_BASE+0x0D8)
|
|
#define CSM_G3_COEF_REG_CH2 (CSM_BASE+0x0DC)
|
|
#define CSM_B_OFST_REG_CH2 (CSM_BASE+0x0E0)
|
|
#define CSM_B1_COEF_REG_CH2 (CSM_BASE+0x0E4)
|
|
#define CSM_B2_COEF_REG_CH2 (CSM_BASE+0x0E8)
|
|
#define CSM_B3_COEF_REG_CH2 (CSM_BASE+0x0EC)
|
|
// Gamma96
|
|
#define GAMMA96_BASE (ISP_BASE_ADDR+0x61000)
|
|
#define GAMMA96_LINE0_DAT0 (GAMMA96_BASE+0x0)
|
|
|
|
// RGB2YC
|
|
#define RGB2YC_BASE (ISP_BASE_ADDR+0x62000)
|
|
|
|
|
|
// Demoire
|
|
#define DEMOIRE_BASE (ISP_BASE_ADDR+0x63000)
|
|
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
|
|
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
|
|
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
|
|
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
|
|
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
|
|
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
|
|
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
|
|
|
|
// CC
|
|
#define CC_BASE (ISP_BASE_ADDR+0x71000)
|
|
#define CC_EN_REG (CC_BASE+0x000)
|
|
#define CC_HUE_OFST (CC_BASE+0x018)
|
|
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
|
|
#define CC_HH_H1_SATRT (CC_BASE+0x200)
|
|
#define CC_HH_H1_END (CC_BASE+0x204)
|
|
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
|
|
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
|
|
#define CC_HH_H1_DMAX (CC_BASE+0x210)
|
|
#define CC_HH_H1_K1 (CC_BASE+0x214)
|
|
#define CC_HH_H1_K2 (CC_BASE+0x218)
|
|
|
|
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
|
|
#define CC_HH_H2_END (CC_BASE+0x220)
|
|
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
|
|
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
|
|
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
|
|
#define CC_HH_H2_K1 (CC_BASE+0x230)
|
|
#define CC_HH_H2_K2 (CC_BASE+0x234)
|
|
|
|
#define CC_HH_H3_SATRT (CC_BASE+0x240)
|
|
#define CC_HH_H3_END (CC_BASE+0x244)
|
|
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
|
|
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
|
|
#define CC_HH_H3_DMAX (CC_BASE+0x250)
|
|
#define CC_HH_H3_K1 (CC_BASE+0x254)
|
|
#define CC_HH_H3_K2 (CC_BASE+0x258)
|
|
|
|
#define CC_HH_H4_SATRT (CC_BASE+0x25C)
|
|
#define CC_HH_H4_END (CC_BASE+0x260)
|
|
#define CC_HH_H4_MAX1 (CC_BASE+0x264)
|
|
#define CC_HH_H4_MAX2 (CC_BASE+0x268)
|
|
#define CC_HH_H4_DMAX (CC_BASE+0x26C)
|
|
#define CC_HH_H4_K1 (CC_BASE+0x270)
|
|
#define CC_HH_H4_K2 (CC_BASE+0x274)
|
|
|
|
#define CC_HH_H5_SATRT (CC_BASE+0x280)
|
|
#define CC_HH_H5_END (CC_BASE+0x284)
|
|
#define CC_HH_H5_MAX1 (CC_BASE+0x288)
|
|
#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
|
|
#define CC_HH_H5_DMAX (CC_BASE+0x290)
|
|
#define CC_HH_H5_K1 (CC_BASE+0x294)
|
|
#define CC_HH_H5_K2 (CC_BASE+0x298)
|
|
|
|
#define CC_HH_H6_SATRT (CC_BASE+0x29C)
|
|
#define CC_HH_H6_END (CC_BASE+0x2A0)
|
|
#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
|
|
#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
|
|
#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
|
|
#define CC_HH_H6_K1 (CC_BASE+0x2B0)
|
|
#define CC_HH_H6_K2 (CC_BASE+0x2B4)
|
|
|
|
|
|
|
|
|
|
// Y_Gamma
|
|
#define YGAMMA_BASE (ISP_BASE_ADDR+0x72000)
|
|
#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
|
|
#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
|
|
|
|
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
|
|
#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
|
|
|
|
//Y_hist
|
|
#define YHIST_BASE (ISP_BASE_ADDR+0x73000)
|
|
#define YHIST_CNT0 (YHIST_BASE+0x000)
|
|
|
|
//C_tran
|
|
#define CTRAN_BASE (ISP_BASE_ADDR+0x74000)
|
|
#define CTRAN_BUF_SW (CTRAN_BASE+0x000)
|
|
#define CTRAN_BUF_SW_STATE (CTRAN_BASE+0x004)
|
|
#define TRAN_LINE0_DAT0 (CTRAN_BASE+0x040)
|
|
|
|
#define TRAN_LINE1_DAT0 (CTRAN_BASE+0x080)
|
|
|
|
|
|
// Sharpness
|
|
#define SHARPEN_BASE (ISP_BASE_ADDR+0x75000)
|
|
|
|
#define SHARPEN_YMTH1 (SHARPEN_BASE+0x000)
|
|
#define SHARPEN_YMTH2 (SHARPEN_BASE+0x004)
|
|
#define SHARPEN_YM_K (SHARPEN_BASE+0x008)
|
|
#define SHARPEN_KM0 (SHARPEN_BASE+0x00C)
|
|
#define SHARPEN_WM0 (SHARPEN_BASE+0x010)
|
|
#define SHARPEN_WM1 (SHARPEN_BASE+0x014)
|
|
#define SHARPEN_WM2 (SHARPEN_BASE+0x018)
|
|
#define SHARPEN_WM3 (SHARPEN_BASE+0x01C)
|
|
#define SHARPEN_WM4 (SHARPEN_BASE+0x020)
|
|
#define SHARPEN_WM5 (SHARPEN_BASE+0x024)
|
|
|
|
#define SHARPEN_YMDTH1 (SHARPEN_BASE+0x040)
|
|
#define SHARPEN_YMDTH2 (SHARPEN_BASE+0x044)
|
|
#define SHARPEN_YMD_K (SHARPEN_BASE+0x048)
|
|
#define SHARPEN_KMD_MAX (SHARPEN_BASE+0x04C)
|
|
#define SHARPEN_WMD0 (SHARPEN_BASE+0x050)
|
|
#define SHARPEN_WMD1 (SHARPEN_BASE+0x054)
|
|
#define SHARPEN_WMD2 (SHARPEN_BASE+0x058)
|
|
#define SHARPEN_WMD3 (SHARPEN_BASE+0x05C)
|
|
#define SHARPEN_WMD4 (SHARPEN_BASE+0x060)
|
|
#define SHARPEN_WMD5 (SHARPEN_BASE+0x064)
|
|
|
|
#define SHARPEN_YHTH1 (SHARPEN_BASE+0x080)
|
|
#define SHARPEN_YHTH2 (SHARPEN_BASE+0x084)
|
|
#define SHARPEN_YH_K (SHARPEN_BASE+0x088)
|
|
#define SHARPEN_KH0 (SHARPEN_BASE+0x08C)
|
|
#define SHARPEN_WH0 (SHARPEN_BASE+0x090)
|
|
#define SHARPEN_WH1 (SHARPEN_BASE+0x094)
|
|
#define SHARPEN_WH2 (SHARPEN_BASE+0x098)
|
|
#define SHARPEN_WH3 (SHARPEN_BASE+0x09C)
|
|
#define SHARPEN_WH4 (SHARPEN_BASE+0x0A0)
|
|
#define SHARPEN_WH5 (SHARPEN_BASE+0x0A4)
|
|
|
|
#define SHARPEN_YHDTH1 (SHARPEN_BASE+0x0C0)
|
|
#define SHARPEN_YHDTH2 (SHARPEN_BASE+0x0C4)
|
|
#define SHARPEN_YHD_K (SHARPEN_BASE+0x0C8)
|
|
#define SHARPEN_KHD_MAX (SHARPEN_BASE+0x0CC)
|
|
#define SHARPEN_WHD0 (SHARPEN_BASE+0x0D0)
|
|
#define SHARPEN_WHD1 (SHARPEN_BASE+0x0D4)
|
|
#define SHARPEN_WHD2 (SHARPEN_BASE+0x0D8)
|
|
#define SHARPEN_WHD3 (SHARPEN_BASE+0x0DC)
|
|
#define SHARPEN_WHD4 (SHARPEN_BASE+0x0E0)
|
|
#define SHARPEN_WHD5 (SHARPEN_BASE+0x0E4)
|
|
|
|
#define SHARPEN_KH00 (SHARPEN_BASE+0x100)
|
|
#define SHARPEN_KH01 (SHARPEN_BASE+0x104)
|
|
#define SHARPEN_KL00 (SHARPEN_BASE+0x108)
|
|
#define SHARPEN_KL01 (SHARPEN_BASE+0x10C)
|
|
#define SHARPEN_KH1 (SHARPEN_BASE+0x110)
|
|
#define SHARPEN_KL1 (SHARPEN_BASE+0x114)
|
|
#define SHARPEN_DLTMAX (SHARPEN_BASE+0x118)
|
|
#define SHARPEN_DFKD (SHARPEN_BASE+0x11C)
|
|
#define SHARPEN_DFMAX (SHARPEN_BASE+0x120)
|
|
|
|
#define SHARPEN_ENH_STREN (SHARPEN_BASE+0x130)
|
|
#define SHARPEN_ENH_THR (SHARPEN_BASE+0x134)
|
|
#define SHARPEN_ENH_GMAX (SHARPEN_BASE+0x138)
|
|
|
|
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+0x140)
|
|
|
|
#define SHARPEN_C_KR1 (SHARPEN_BASE+0x1C0)
|
|
#define SHARPEN_C_KR2 (SHARPEN_BASE+0x1C4)
|
|
#define SHARPEN_C_KG1 (SHARPEN_BASE+0x1C8)
|
|
#define SHARPEN_C_KG2 (SHARPEN_BASE+0x1CC)
|
|
#define SHARPEN_C_KB1 (SHARPEN_BASE+0x1D0)
|
|
#define SHARPEN_C_KB2 (SHARPEN_BASE+0x1D4)
|
|
#define SHARPEN_C_ZONE_EN (SHARPEN_BASE+0x1D8)
|
|
#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1DC)
|
|
#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1E0)
|
|
#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1E4)
|
|
#define SHARPEN_C_FLT_SEL (SHARPEN_BASE+0x1E8)
|
|
|
|
#define SHARPEN_C_SAT_DAT0 (SHARPEN_BASE+0x200)
|
|
|
|
// sharpen_ch2
|
|
#define SHARPEN_YMTH1_CH2 (SHARPEN_BASE+0x280)
|
|
#define SHARPEN_YMTH2_CH2 (SHARPEN_BASE+0x284)
|
|
#define SHARPEN_YM_K_CH2 (SHARPEN_BASE+0x288)
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#define SHARPEN_KM0_CH2 (SHARPEN_BASE+0x28C)
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#define SHARPEN_YMDTH1_CH2 (SHARPEN_BASE+0x290)
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#define SHARPEN_YMDTH2_CH2 (SHARPEN_BASE+0x294)
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#define SHARPEN_YMD_K_CH2 (SHARPEN_BASE+0x298)
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#define SHARPEN_KMDMAX_CH2 (SHARPEN_BASE+0x29C)
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#define SHARPEN_YHTH1_CH2 (SHARPEN_BASE+0x2a0)
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#define SHARPEN_YHTH2_CH2 (SHARPEN_BASE+0x2a4)
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#define SHARPEN_YH_K_CH2 (SHARPEN_BASE+0x2a8)
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#define SHARPEN_KH0_CH2 (SHARPEN_BASE+0x2aC)
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#define SHARPEN_YHDTH1_CH2 (SHARPEN_BASE+0x2b0)
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#define SHARPEN_YHDTH2_CH2 (SHARPEN_BASE+0x2b4)
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#define SHARPEN_YHD_K_CH2 (SHARPEN_BASE+0x2b8)
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#define SHARPEN_KHDMAX_CH2 (SHARPEN_BASE+0x2bC)
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#define SHARPEN_DFKD_CH2 (SHARPEN_BASE+0x2c0)
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#define SHARPEN_DFMAX_CH2 (SHARPEN_BASE+0x2c4)
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#define SHARPEN_EN_CH1 (SHARPEN_BASE+0x240)
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#define SHARPEN_EN_CH2 (SHARPEN_BASE+0x244)
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#define DENOISE_EN_CH1 (SHARPEN_BASE+0x248)
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#define DENOISE_EN_CH2 (SHARPEN_BASE+0x24C)
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#define NOISETHR_CH1 (SHARPEN_BASE+0x250)
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#define NOISETHR_CH2 (SHARPEN_BASE+0x254)
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// YC_Gain
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#define YC_GAIN_BASE 0x30076000
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#define Y_GAIN (YC_GAIN_BASE+(0x000))
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#define CB_GAIN (YC_GAIN_BASE+(0x004))
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#define CR_GAIN (YC_GAIN_BASE+(0x008))
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#define Y_OFST (YC_GAIN_BASE+(0x00C))
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#define Y_MAX_THD (YC_GAIN_BASE+(0x010))
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#define Y_MIN_THD (YC_GAIN_BASE+(0x014))
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//PLL use to upscaler
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#define PLL_BASE 0x20000000
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#define PLL_SYSCTRLREG_LOCK (PLL_BASE+0x002C)
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#define PLLB1_CTRL (PLL_BASE+0x000C)
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#define PLLB2_CTRL (PLL_BASE+0x0010)
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#define PLLB_CTRL (PLL_BASE+0x0014)
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#endif
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