mirror of https://github.com/OpenIPC/firmware.git
564 lines
20 KiB
C
564 lines
20 KiB
C
#ifndef _XM510_REG_
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#define _XM510_REG_
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#define DDR_BASE_ADDR (0x80000000)
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#define VIDOEMODE_BASE 0x40000000
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#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
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#define VI_VH_NUM (VIDOEMODE_BASE+0x090)
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#define VI_VH_ALL (VIDOEMODE_BASE+0x094)
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// DPC
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#define SDPC_BASE 0x40003000
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#define SDPC_CLK_SW (SDPC_BASE+0x000)
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#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
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#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
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#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
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#define DDPC_BASE 0x40023000
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#define DDPC_MAX_THD (DDPC_BASE+0x000)
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#define DDPC_MIN_THD (DDPC_BASE+0x004)
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#define DDPC_DIFF_THD (DDPC_BASE+0x008)
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// BlackLevel
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#define BLACKLEVEL_BASE 0x40004000
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#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
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#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
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#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
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// front Gamma
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#define FRONTGAMMA_BASE 0x40005000
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//LSC
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#define LSC_BASE 0x40006000
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#define LSC_CTRL (LSC_BASE+0x000)
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//NR_2D
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#define NR_2D_BASE 0x40020000
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#define NR_2D_FLT_EN (NR_2D_BASE + 0x018)
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#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
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#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
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#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
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#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
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#define NR_2D_COEF_SEL_REG (NR_2D_BASE + 0x010)
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#define NR_2D_DELTA_THD (NR_2D_BASE + 0x014)
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//NR_3D
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#define NR_3D_BASE 0x40040000
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#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
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#define NR_3D_RAMP (NR_3D_BASE + 0x004)
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#define NR_3D_G1AMP (NR_3D_BASE + 0x008)
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#define NR_3D_G2AMP (NR_3D_BASE + 0x00C)
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#define NR_3D_BAMP (NR_3D_BASE + 0x010)
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#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
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#define NR_3D_NR_LEVEL (NR_3D_BASE + 0x018)
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#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
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#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
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#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
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#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
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#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
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#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
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#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
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#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
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#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
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#define NR_3D_DDR_HNUM (NR_3D_BASE + 0x0D0)
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#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
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#define NR_3D_YCTRL_ERR70 (NR_3D_BASE + 0x0D8)
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#define NR_3D_YCTRL_ERRF8 (NR_3D_BASE + 0x0DC)
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#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
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#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
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#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
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#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
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#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
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#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
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#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
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#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
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#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
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#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
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#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
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#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
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#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
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#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
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#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
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#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
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//Bayer_Dec
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#define BD_BASE 0x40050000
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#define BD_PIC_ALL_PIXELS (BD_BASE+0x000)
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#define BD_PIC_ALL_LINES (BD_BASE+0x004)
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#define BD_PIC_HNUM (BD_BASE+0x008)
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#define BD_PIC_VNUM (BD_BASE+0x00C)
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#define BD_PASSTHROUGH_MODE1 (BD_BASE+0x010)
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#define BD_PASSTHROUGH_MODE2 (BD_BASE+0x014)
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//VideoFetch
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#define VF_BASE 0x40051000
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#define VF_BAYER_ADDR0 (VF_BASE+0x000)
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#define VF_BAYER_ADDR1 (VF_BASE+0x004)
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#define VF_BAYER_ADDR2 (VF_BASE+0x008)
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#define VF_BAYER_ADDR3 (VF_BASE+0x00C)
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#define VF_BAYER_ADDR4 (VF_BASE+0x010)
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#define VF_BAYER_ADDR5 (VF_BASE+0x014)
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#define VF_BAYER_ADDR6 (VF_BASE+0x018)
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#define VF_BAYER_ADDR7 (VF_BASE+0x01C)
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#define VF_BAYER_ADDR0_END (VF_BASE+0x020)
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#define VF_BAYER_ADDR1_END (VF_BASE+0x024)
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#define VF_BAYER_ADDR2_END (VF_BASE+0x028)
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#define VF_BAYER_ADDR3_END (VF_BASE+0x02C)
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#define VF_BAYER_ADDR4_END (VF_BASE+0x030)
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#define VF_BAYER_ADDR5_END (VF_BASE+0x034)
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#define VF_BAYER_ADDR6_END (VF_BASE+0x038)
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#define VF_BAYER_ADDR7_END (VF_BASE+0x03C)
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#define VF_LINE_ADDR_INC (VF_BASE+0x040)
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#define VF_BAYER_INV (VF_BASE+0x044)
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#define VF_TOTAL_FRAME_NUM (VF_BASE+0x048)
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#define VF_LINE_NUM_PIX (VF_BASE+0x04C)
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#define VF_ENABLE (VF_BASE+0x050)
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//AWB
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#define AWB_BASE 0x40010000
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#define AWB_FRONTGAIN_R (AWB_BASE + 0x5000)
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#define AWB_FRONTGAIN_G (AWB_BASE + 0x5004)
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#define AWB_FRONTGAIN_B (AWB_BASE + 0x5008)
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#define AWB_BACKGAIN_RGAIN_RR (AWB_BASE + 0x0000)
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#define AWB_BACKGAIN_RGAIN_RG (AWB_BASE + 0x0004)
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#define AWB_BACKGAIN_RGAIN_BG (AWB_BASE + 0x0008)
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#define AWB_BACKGAIN_RGAIN_BB (AWB_BASE + 0x000C)
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#define AWB_BACKGAIN_BGAIN_RR (AWB_BASE + 0x0010)
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#define AWB_BACKGAIN_BGAIN_RG (AWB_BASE + 0x0014)
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#define AWB_BACKGAIN_BGAIN_BG (AWB_BASE + 0x0018)
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#define AWB_BACKGAIN_BGAIN_BB (AWB_BASE + 0x001C)
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#define AWB_BACKGAIN_LIMITMAX (AWB_BASE + 0x0020)
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#define AWB_BACKGAIN_LIMITMIN (AWB_BASE + 0x0024)
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#define AWB_CSM_BUF_SW (AWB_BASE+0x1000)
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#define AWB_CSM_BUF_SW_STATE (AWB_BASE+0x1004)
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#define AWB_CSM_R_OFST_REG0 (AWB_BASE+0x1040)
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#define AWB_CSM_R1_COEF_REG0 (AWB_BASE+0x1044)
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#define AWB_CSM_R2_COEF_REG0 (AWB_BASE+0x1048)
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#define AWB_CSM_R3_COEF_REG0 (AWB_BASE+0x104C)
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#define AWB_CSM_G_OFST_REG0 (AWB_BASE+0x1050)
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#define AWB_CSM_G1_COEF_REG0 (AWB_BASE+0x1054)
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#define AWB_CSM_G2_COEF_REG0 (AWB_BASE+0x1058)
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#define AWB_CSM_G3_COEF_REG0 (AWB_BASE+0x105C)
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#define AWB_CSM_B_OFST_REG0 (AWB_BASE+0x1060)
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#define AWB_CSM_B1_COEF_REG0 (AWB_BASE+0x1064)
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#define AWB_CSM_B2_COEF_REG0 (AWB_BASE+0x1068)
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#define AWB_CSM_B3_COEF_REG0 (AWB_BASE+0x106C)
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#define AWB_CSM_R_OFST_REG1 (AWB_BASE+0x1080)
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#define AWB_CSM_R1_COEF_REG1 (AWB_BASE+0x1084)
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#define AWB_CSM_R2_COEF_REG1 (AWB_BASE+0x1088)
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#define AWB_CSM_R3_COEF_REG1 (AWB_BASE+0x108C)
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#define AWB_CSM_G_OFST_REG1 (AWB_BASE+0x1090)
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#define AWB_CSM_G1_COEF_REG1 (AWB_BASE+0x1094)
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#define AWB_CSM_G2_COEF_REG1 (AWB_BASE+0x1098)
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#define AWB_CSM_G3_COEF_REG1 (AWB_BASE+0x109C)
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#define AWB_CSM_B_OFST_REG1 (AWB_BASE+0x10A0)
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#define AWB_CSM_B1_COEF_REG1 (AWB_BASE+0x10A4)
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#define AWB_CSM_B2_COEF_REG1 (AWB_BASE+0x10A8)
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#define AWB_CSM_B3_COEF_REG1 (AWB_BASE+0x10AC)
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#define AWB_GAMMA30_BUF_SW (AWB_BASE + 0x2000)
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#define AWB_GAMMA30_SW_STATE (AWB_BASE + 0x2004)
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#define AWB_GAMMA30_LINE0_DAT0 (AWB_BASE + 0x2040)
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#define AWB_GAMMA30_LINE1_DAT0 (AWB_BASE + 0x20C0)
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#define AWB_RGBMAX_REG (AWB_BASE + 0x500C)
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// AWB (RGB2YC)
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#define AWB_RGB2YC_COEF_Y1 (AWB_BASE + 0x3000)
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#define AWB_RGB2YC_COEF_Y2 (AWB_BASE + 0x3004)
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#define AWB_RGB2YC_COEF_Y3 (AWB_BASE + 0x3008)
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#define AWB_RGB2YC_COEF_CB1 (AWB_BASE + 0x300C)
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#define AWB_RGB2YC_COEF_CB2 (AWB_BASE + 0x3010)
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#define AWB_RGB2YC_COEF_CB3 (AWB_BASE + 0x3014)
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#define AWB_RGB2YC_COEF_CR1 (AWB_BASE + 0x3018)
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#define AWB_RGB2YC_COEF_CR2 (AWB_BASE + 0x301C)
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#define AWB_RGB2YC_COEF_CR3 (AWB_BASE + 0x3020)
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#define AWB_RGB2YC_OFST_Y (AWB_BASE + 0x3024)
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#define AWB_RGB2YC_OFST_CB (AWB_BASE + 0x3028)
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#define AWB_RGB2YC_OFST_CR (AWB_BASE + 0x302C)
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#define AWB_WDW_VBEGIN (AWB_BASE + 0x4000)
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#define AWB_WDW_VEND (AWB_BASE + 0x4004)
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#define AWB_WDW_HBEGIN (AWB_BASE + 0x4008)
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#define AWB_WDW_HEND (AWB_BASE + 0x400C)
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#define AWB_FACT_LH (AWB_BASE + 0x4040)
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#define AWB_FACT_LV (AWB_BASE + 0x4044)
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#define AWB_FACT_L45 (AWB_BASE + 0x4048)
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#define AWB_FACT_L135 (AWB_BASE + 0x404C)
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#define AWB_FACT_RGBTHD (AWB_BASE + 0x4050)
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#define AWB_FACT_YTHD (AWB_BASE + 0x4054)
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#define AWB_FACT_KCBCR1 (AWB_BASE + 0x4058)
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#define AWB_FACT_KCBCR2 (AWB_BASE + 0x405C)
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#define AWB_FACT_KCBCR3 (AWB_BASE + 0x4060)
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#define AWB_FACT_KCBCR4 (AWB_BASE + 0x4064)
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#define AWB_CH1_M_WPCNT (AWB_BASE + 0x40C0)
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#define AWB_CH1_M_CBSUM (AWB_BASE + 0x40C4)
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#define AWB_CH1_M_CRSUM (AWB_BASE + 0x40C8)
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#define AWB_CH2_M_WPCNT (AWB_BASE + 0x4100)
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#define AWB_CH2_M_CBSUM (AWB_BASE + 0x4104)
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#define AWB_CH2_M_CRSUM (AWB_BASE + 0x4108)
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#define AWB_CH3_M_WPCNT (AWB_BASE + 0x4140)
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#define AWB_CH3_M_CBSUM (AWB_BASE + 0x4144)
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#define AWB_CH3_M_CRSUM (AWB_BASE + 0x4148)
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#define AWB_CH4_M_WPCNT (AWB_BASE + 0x4180)
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#define AWB_CH4_M_CBSUM (AWB_BASE + 0x4184)
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#define AWB_CH4_M_CRSUM (AWB_BASE + 0x4188)
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//AF
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#define AF_BASE 0x40021000
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#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
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#define AF_WDW0_VEND (AF_BASE + 0x004)
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#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
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#define AF_WDW0_HEND (AF_BASE + 0x00C)
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#define AF_WDW0_HZ (AF_BASE + 0x094)
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//AE
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#define AE_BASEADDR 0x40030000
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#define AE_WINDOW_VSTART (AE_BASEADDR + 0x3000)
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#define AE_WINDOW_HSTART (AE_BASEADDR + 0x3020)
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#define AE_WINDOWY_ROW1 (AE_BASEADDR + 0x3100)
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#define AE_WINDOWY_ROW2 (AE_BASEADDR + 0x311C)
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#define AE_WINDOWY_ROW3 (AE_BASEADDR + 0x3140)
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#define AE_WINDOWY_ROW4 (AE_BASEADDR + 0x315C)
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#define AE_WINDOWY_ROW5 (AE_BASEADDR + 0x3180)
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#define AE_WINDOWY_ROW6 (AE_BASEADDR + 0x319C)
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#define AE_WINDOWY_ROW7 (AE_BASEADDR + 0x31C0)
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#define AE_HIST_COUNT (AE_BASEADDR + 0x3080)
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// Demosaic
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#define DEMOSAIC_BASE 0x40052000
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#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
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#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
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#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
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// CSM
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#define CSM_GAMMA_BYPASS 0x40060004
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#define CSM_BASE 0x40061000
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#define CSM_BUF_SW (CSM_BASE+0x000)
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#define CSM_BUF_SW_STATE (CSM_BASE+0x004)
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#define CSM_R_OFST_REG0 (CSM_BASE+0x040)
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#define CSM_R1_COEF_REG0 (CSM_BASE+0x044)
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#define CSM_R2_COEF_REG0 (CSM_BASE+0x048)
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#define CSM_R3_COEF_REG0 (CSM_BASE+0x04C)
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#define CSM_G_OFST_REG0 (CSM_BASE+0x050)
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#define CSM_G1_COEF_REG0 (CSM_BASE+0x054)
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#define CSM_G2_COEF_REG0 (CSM_BASE+0x058)
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#define CSM_G3_COEF_REG0 (CSM_BASE+0x05C)
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#define CSM_B_OFST_REG0 (CSM_BASE+0x060)
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#define CSM_B1_COEF_REG0 (CSM_BASE+0x064)
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#define CSM_B2_COEF_REG0 (CSM_BASE+0x068)
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#define CSM_B3_COEF_REG0 (CSM_BASE+0x06C)
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#define CSM_R_OFST_REG1 (CSM_BASE+0x080)
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#define CSM_R1_COEF_REG1 (CSM_BASE+0x084)
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#define CSM_R2_COEF_REG1 (CSM_BASE+0x088)
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#define CSM_R3_COEF_REG1 (CSM_BASE+0x08C)
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#define CSM_G_OFST_REG1 (CSM_BASE+0x090)
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#define CSM_G1_COEF_REG1 (CSM_BASE+0x094)
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#define CSM_G2_COEF_REG1 (CSM_BASE+0x098)
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#define CSM_G3_COEF_REG1 (CSM_BASE+0x09C)
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#define CSM_B_OFST_REG1 (CSM_BASE+0x0A0)
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#define CSM_B1_COEF_REG1 (CSM_BASE+0x0A4)
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#define CSM_B2_COEF_REG1 (CSM_BASE+0x0A8)
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#define CSM_B3_COEF_REG1 (CSM_BASE+0x0AC)
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// Gamma60
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#define GAMMA60_BASE 0x40062000
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#define GAMMA60_BUF_SW (GAMMA60_BASE+0x000)
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#define GAMMA60_BUF_SW_STATE (GAMMA60_BASE+0x004)
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#define GAMMA60_LINE0_DAT0 (GAMMA60_BASE+0x040)
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#define GAMMA60_LINE1_DAT0 (GAMMA60_BASE+0x140)
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// RGB2YC
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#define RGB2YC_BASE 0x40065000
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// Demoire
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#define DEMOIRE_BASE 0x40067000
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#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
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#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
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#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
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#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
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#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
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#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
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#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
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// Upscaler
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#define UPSCALER_BASE 0x40070000
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#define UPSCALER_XDELTA (UPSCALER_BASE+0x000)
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#define UPSCALER_YDELTA (UPSCALER_BASE+0x004)
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#define UPSCALER_XSTART0 (UPSCALER_BASE+0x008)
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#define UPSCALER_YSTART0 (UPSCALER_BASE+0x00C)
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#define UPSCALER_XPHI0 (UPSCALER_BASE+0x010)
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#define UPSCALER_YPHI0 (UPSCALER_BASE+0x014)
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#define UPSCALER_XPHI_OFFSET (UPSCALER_BASE+0x018)
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#define UPSCALER_YPHI_OFFSET (UPSCALER_BASE+0x01C)
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#define UPSCALER_XSTART_OFFSET (UPSCALER_BASE+0x020)
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#define UPSCALER_YSTART_OFFSET (UPSCALER_BASE+0x024)
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#define UPSCALER_TOTAL_HNUM (UPSCALER_BASE+0x030)
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#define UPSCALER_TOTAL_VNUM (UPSCALER_BASE+0x034)
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#define UPSCALER_ACTIVE_HNUM (UPSCALER_BASE+0x038)
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#define UPSCALER_ACTIVE_VNUM (UPSCALER_BASE+0x03C)
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// CC
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#define CC_BASE 0x40071000
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#define CC_EN_REG (CC_BASE+0x000)
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#define CC_HUE_OFST (CC_BASE+0x018)
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#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
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#define CC_HS_TRAN_DAT1 (CC_BASE+0x0E8)
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#define CC_HH_H1_SATRT (CC_BASE+0x200)
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#define CC_HH_H1_END (CC_BASE+0x204)
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#define CC_HH_H1_MAX1 (CC_BASE+0x208)
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#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
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#define CC_HH_H1_DMAX (CC_BASE+0x210)
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#define CC_HH_H1_K1 (CC_BASE+0x214)
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#define CC_HH_H1_K2 (CC_BASE+0x218)
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#define CC_HH_H2_SATRT (CC_BASE+0x21C)
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#define CC_HH_H2_END (CC_BASE+0x220)
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#define CC_HH_H2_MAX1 (CC_BASE+0x224)
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#define CC_HH_H2_MAX2 (CC_BASE+0x228)
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#define CC_HH_H2_DMAX (CC_BASE+0x22C)
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#define CC_HH_H2_K1 (CC_BASE+0x230)
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#define CC_HH_H2_K2 (CC_BASE+0x234)
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#define CC_HH_H3_SATRT (CC_BASE+0x240)
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#define CC_HH_H3_END (CC_BASE+0x244)
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#define CC_HH_H3_MAX1 (CC_BASE+0x248)
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#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
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#define CC_HH_H3_DMAX (CC_BASE+0x250)
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#define CC_HH_H3_K1 (CC_BASE+0x254)
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#define CC_HH_H3_K2 (CC_BASE+0x258)
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#define CC_HH_H4_SATRT (CC_BASE+0x25C)
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#define CC_HH_H4_END (CC_BASE+0x260)
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#define CC_HH_H4_MAX1 (CC_BASE+0x264)
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#define CC_HH_H4_MAX2 (CC_BASE+0x268)
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#define CC_HH_H4_DMAX (CC_BASE+0x26C)
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#define CC_HH_H4_K1 (CC_BASE+0x270)
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#define CC_HH_H4_K2 (CC_BASE+0x274)
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#define CC_HH_H5_SATRT (CC_BASE+0x280)
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#define CC_HH_H5_END (CC_BASE+0x284)
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#define CC_HH_H5_MAX1 (CC_BASE+0x288)
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#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
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#define CC_HH_H5_DMAX (CC_BASE+0x290)
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#define CC_HH_H5_K1 (CC_BASE+0x294)
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#define CC_HH_H5_K2 (CC_BASE+0x298)
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#define CC_HH_H6_SATRT (CC_BASE+0x29C)
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#define CC_HH_H6_END (CC_BASE+0x2A0)
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#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
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#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
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#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
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#define CC_HH_H6_K1 (CC_BASE+0x2B0)
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#define CC_HH_H6_K2 (CC_BASE+0x2B4)
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// Y_Gamma
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#define YGAMMA_BASE 0x40072000
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#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
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#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
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#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
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#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
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#define YHIST_BASE (0x40073000)
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#define YHIST_CNT0 (YHIST_BASE+0x000)
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#define CTRAN_BASE 0x40074000
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// Sharpness
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#define SHARPEN_BASE 0x40075000
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#define SHARPEN_H00_SEL (SHARPEN_BASE+(0x04))
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#define SHARPEN_KH1 (SHARPEN_BASE+(0x08))
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#define SHARPEN_KL1 (SHARPEN_BASE+(0x0C))
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#define SHARPEN_DMAX (SHARPEN_BASE+(0x010))
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#define SHARPEN_KD (SHARPEN_BASE+(0x018))
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#define SHARPEN_KD_MAX (SHARPEN_BASE+(0x01C))
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#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+(0x020))
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#define SHARPEN_YMTH1 (SHARPEN_BASE+(0x128))
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#define SHARPEN_YMTH2 (SHARPEN_BASE+(0x12C))
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#define SHARPEN_KKM (SHARPEN_BASE+(0x130))
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|
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#define SHARPEN_WM0 (SHARPEN_BASE+(0x134))
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#define SHARPEN_WM1 (SHARPEN_BASE+(0x138))
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#define SHARPEN_WM2 (SHARPEN_BASE+(0x13C))
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#define SHARPEN_WM3 (SHARPEN_BASE+(0x140))
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#define SHARPEN_WM4 (SHARPEN_BASE+(0x144))
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#define SHARPEN_WM5 (SHARPEN_BASE+(0x148))
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#define SHARPEN_KM0 (SHARPEN_BASE+(0x14c))
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|
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#define SHARPEN_YHTH1 (SHARPEN_BASE+(0x150))
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#define SHARPEN_YHTH2 (SHARPEN_BASE+(0x154))
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#define SHARPEN_KKH (SHARPEN_BASE+(0x158))
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#define SHARPEN_WH0 (SHARPEN_BASE+(0x15C))
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#define SHARPEN_WH1 (SHARPEN_BASE+(0x160))
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#define SHARPEN_WH2 (SHARPEN_BASE+(0x164))
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#define SHARPEN_WH3 (SHARPEN_BASE+(0x168))
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#define SHARPEN_WH4 (SHARPEN_BASE+(0x16C))
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#define SHARPEN_WH5 (SHARPEN_BASE+(0x170))
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#define SHARPEN_KH0 (SHARPEN_BASE+(0x174))
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|
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#define SHARPEN_YMDTH1 (SHARPEN_BASE+(0x178))
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#define SHARPEN_YMDTH2 (SHARPEN_BASE+(0x17C))
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#define SHARPEN_KKMD (SHARPEN_BASE+(0x180))
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|
|
|
#define SHARPEN_WMD0 (SHARPEN_BASE+(0x184))
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#define SHARPEN_WMD1 (SHARPEN_BASE+(0x188))
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#define SHARPEN_WMD2 (SHARPEN_BASE+(0x18C))
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|
#define SHARPEN_WMD3 (SHARPEN_BASE+(0x190))
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|
#define SHARPEN_WMD4 (SHARPEN_BASE+(0x194))
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|
#define SHARPEN_WMD5 (SHARPEN_BASE+(0x198))
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|
#define SHARPEN_KMD_MAX (SHARPEN_BASE+(0x19C))
|
|
|
|
#define SHARPEN_YHDTH1 (SHARPEN_BASE+(0x1A0))
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|
#define SHARPEN_YHDTH2 (SHARPEN_BASE+(0x1A4))
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|
#define SHARPEN_KKHD (SHARPEN_BASE+(0x1A8))
|
|
|
|
#define SHARPEN_WHD0 (SHARPEN_BASE+(0x1AC))
|
|
#define SHARPEN_WHD1 (SHARPEN_BASE+(0x1B0))
|
|
#define SHARPEN_WHD2 (SHARPEN_BASE+(0x1B4))
|
|
#define SHARPEN_WHD3 (SHARPEN_BASE+(0x1B8))
|
|
#define SHARPEN_WHD4 (SHARPEN_BASE+(0x1BC))
|
|
#define SHARPEN_WHD5 (SHARPEN_BASE+(0x1C0))
|
|
#define SHARPEN_KHD_MAX (SHARPEN_BASE+(0x1C4))
|
|
|
|
#define SHARPEN_KCMIN (SHARPEN_BASE+(0x1E8))
|
|
#define SHARPEN_ENABLE (SHARPEN_BASE+(0x204))
|
|
#define SHARPEN_CBCR_ENABLE (SHARPEN_BASE+(0x208))
|
|
|
|
// YC_Gain
|
|
#define YC_GAIN_BASE 0x40076000
|
|
#define Y_GAIN (YC_GAIN_BASE+(0x000))
|
|
#define CB_GAIN (YC_GAIN_BASE+(0x004))
|
|
#define CR_GAIN (YC_GAIN_BASE+(0x008))
|
|
|
|
|
|
// AWB2
|
|
#define AWB2_BASE (0x40016000)
|
|
#define AWB2_WDW_PIXL0 (AWB2_BASE+0x000)
|
|
#define AWB2_WDW_PIXL1 (AWB2_BASE+0x004)
|
|
#define AWB2_WDW_PIXL2 (AWB2_BASE+0x008)
|
|
#define AWB2_WDW_PIXL3 (AWB2_BASE+0x00C)
|
|
#define AWB2_WDW_PIXL4 (AWB2_BASE+0x010)
|
|
#define AWB2_WDW_PIXL5 (AWB2_BASE+0x014)
|
|
#define AWB2_WDW_PIXL6 (AWB2_BASE+0x018)
|
|
#define AWB2_WDW_PIXL7 (AWB2_BASE+0x01C)
|
|
#define AWB2_WDW_PIXL8 (AWB2_BASE+0x020)
|
|
#define AWB2_WDW_PIXL9 (AWB2_BASE+0x024)
|
|
#define AWB2_WDW_PIXL10 (AWB2_BASE+0x028)
|
|
#define AWB2_WDW_PIXL11 (AWB2_BASE+0x02C)
|
|
#define AWB2_WDW_PIXL12 (AWB2_BASE+0x030)
|
|
#define AWB2_WDW_PIXL13 (AWB2_BASE+0x034)
|
|
#define AWB2_WDW_PIXL14 (AWB2_BASE+0x038)
|
|
#define AWB2_WDW_PIXL15 (AWB2_BASE+0x03C)
|
|
#define AWB2_WDW_PIXL16 (AWB2_BASE+0x040)
|
|
#define AWB2_WDW_PIXL17 (AWB2_BASE+0x044)
|
|
#define AWB2_WDW_PIXL18 (AWB2_BASE+0x048)
|
|
#define AWB2_WDW_PIXL19 (AWB2_BASE+0x04C)
|
|
#define AWB2_WDW_PIXL20 (AWB2_BASE+0x050)
|
|
#define AWB2_WDW_PIXL21 (AWB2_BASE+0x054)
|
|
#define AWB2_WDW_PIXL22 (AWB2_BASE+0x058)
|
|
#define AWB2_WDW_PIXL23 (AWB2_BASE+0x05C)
|
|
#define AWB2_WDW_PIXL24 (AWB2_BASE+0x060)
|
|
#define AWB2_WDW_PIXL25 (AWB2_BASE+0x064)
|
|
#define AWB2_WDW_PIXL26 (AWB2_BASE+0x068)
|
|
#define AWB2_WDW_PIXL27 (AWB2_BASE+0x06C)
|
|
#define AWB2_WDW_PIXL28 (AWB2_BASE+0x070)
|
|
#define AWB2_WDW_PIXL29 (AWB2_BASE+0x074)
|
|
#define AWB2_WDW_PIXL30 (AWB2_BASE+0x078)
|
|
#define AWB2_WDW_PIXL31 (AWB2_BASE+0x07C)
|
|
#define AWB2_WDW_PIXL32 (AWB2_BASE+0x080)
|
|
|
|
#define AWB2_WDW_LINE0 (AWB2_BASE+0x0C0)
|
|
#define AWB2_WDW_LINE1 (AWB2_BASE+0x0C4)
|
|
#define AWB2_WDW_LINE2 (AWB2_BASE+0x0C8)
|
|
#define AWB2_WDW_LINE3 (AWB2_BASE+0x0CC)
|
|
#define AWB2_WDW_LINE4 (AWB2_BASE+0x0D0)
|
|
#define AWB2_WDW_LINE5 (AWB2_BASE+0x0D4)
|
|
#define AWB2_WDW_LINE6 (AWB2_BASE+0x0D8)
|
|
#define AWB2_WDW_LINE7 (AWB2_BASE+0x0DC)
|
|
#define AWB2_WDW_LINE8 (AWB2_BASE+0x0E0)
|
|
#define AWB2_WDW_LINE9 (AWB2_BASE+0x0E4)
|
|
#define AWB2_WDW_LINE10 (AWB2_BASE+0x0E8)
|
|
#define AWB2_WDW_LINE11 (AWB2_BASE+0x0EC)
|
|
#define AWB2_WDW_LINE12 (AWB2_BASE+0x0F0)
|
|
#define AWB2_WDW_LINE13 (AWB2_BASE+0x0F4)
|
|
#define AWB2_WDW_LINE14 (AWB2_BASE+0x0F8)
|
|
#define AWB2_WDW_LINE15 (AWB2_BASE+0x0FC)
|
|
#define AWB2_WDW_LINE16 (AWB2_BASE+0x100)
|
|
|
|
#define AWB2_SRAM_ADDR_RC (AWB2_BASE+0x140)
|
|
#define AWB2_SRAM_RD_EN (AWB2_BASE+0x144)
|
|
#define AWB2_R_INTG (AWB2_BASE+0x148)
|
|
#define AWB2_G_INTG (AWB2_BASE+0x14C)
|
|
#define AWB2_B_INTG (AWB2_BASE+0x150)
|
|
|
|
//PLL use to upscaler
|
|
#define PLL_BASE 0x20000000
|
|
#define PLL_SYSCTRLREG_LOCK (PLL_BASE+0x002C)
|
|
|
|
#define PLLB1_CTRL (PLL_BASE+0x000C)
|
|
#define PLLB2_CTRL (PLL_BASE+0x0010)
|
|
#define PLLB_CTRL (PLL_BASE+0x0014)
|
|
|
|
//Video Store
|
|
#define VSTORE_BASE 0x40080000
|
|
#define VSTORE_EN_CH1 (0x40080000+0x1034)
|
|
#define VSTORE_EN_CH2 (0x40080000+0x2034)
|
|
#define VSTORE_EN_CH3 (0x40080000+0x3034)
|
|
|
|
#endif
|
|
|
|
|
|
|