mirror of https://github.com/OpenIPC/firmware.git
68 lines
2.6 KiB
INI
68 lines
2.6 KiB
INI
[sensor]
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Sensor_type=stSnsImx335Obj
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Mode=WDR_MODE_NONE
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DllFile=libsns_imx335.so
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[mode]
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input_mode=INPUT_MODE_MIPI
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raw_bitness=12
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[mipi]
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lane_id = 0|1|2|3|-1|-1|-1|-1| ;lane_id: -1 - disable
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[isp_image]
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Isp_FrameRate=20
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Isp_Bayer=BAYER_RGGB
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[vi_dev]
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Input_mod=VI_MODE_MIPI
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Work_mod = VI_WORK_MODE_1Multiplex
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Mask_num = 2
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Mask_0 = 0xFFF00000
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Mask_1 = 0x0
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Scan_mode = VI_SCAN_PROGRESSIVE
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Data_seq = VI_DATA_SEQ_YUYV
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Vsync =1 ; vertical synchronization signal
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;VI_VSYNC_PULSE,
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VsyncNeg=1 ;Polarity of the vertical synchronization signal
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;VI_VSYNC_NEG_HIGH = 0,
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;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
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Hsync =0 ;Attribute of the horizontal synchronization signal
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;VI_HSYNC_VALID_SINGNAL = 0,
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;VI_HSYNC_PULSE,
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HsyncNeg =0 ;Polarity of the horizontal synchronization signal
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;VI_HSYNC_NEG_HIGH = 0,
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;VI_HSYNC_NEG_LOW
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VsyncValid =1 ;Attribute of the valid vertical synchronization signal
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;VI_VSYNC_NORM_PULSE = 0,
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;VI_VSYNC_VALID_SINGAL,
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VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
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;VI_VSYNC_VALID_NEG_HIGH = 0,
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;VI_VSYNC_VALID_NEG_LOW
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Timingblank_HsyncHfb =0 ;Horizontal front blanking width
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Timingblank_HsyncAct =1280 ;Horizontal effetive width
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Timingblank_HsyncHbb =0 ;Horizontal back blanking width
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Timingblank_VsyncVfb =0 ;Vertical front blanking height
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Timingblank_VsyncVact =720 ;Vertical effetive width
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Timingblank_VsyncVbb=0 ;Vertical back blanking height
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Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
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Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
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Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
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InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
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DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
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DevRect_w=2592
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DevRect_h=1944
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DevRect_x=200
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DevRect_y=20
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Combine_mode =0 ;Y/C composite or separation mode
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;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
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;VI_COMBINE_SEPARATE, /*Separate mode */
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Comp_mode =0 ;Component mode (single-component or dual-component)
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;VI_COMP_MODE_SINGLE = 0, /*single component mode */
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;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
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Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
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;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
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;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
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FullLinesStd=4500
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