mirror of https://github.com/OpenIPC/firmware.git
596 lines
15 KiB
Diff
596 lines
15 KiB
Diff
--- linux-4.9.37/drivers/mtd/spi-nor/goke-sfc.c 1970-01-01 03:00:00.000000000 +0300
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+++ linux-4.9.y/drivers/mtd/spi-nor/goke-sfc.c 2021-06-07 13:01:33.000000000 +0300
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@@ -0,0 +1,592 @@
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+/*
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+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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+ */
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+#include <linux/clk.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/iopoll.h>
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+#include <linux/module.h>
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+#include <linux/mfd/goke_fmc.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/spi-nor.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+#include "../mtdcore.h"
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+
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+#define FMC_OP_DMA 0x68
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+
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+struct fmc_priv {
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+ u32 chipselect;
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+ u32 clkrate;
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+ struct fmc_host *host;
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+};
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+
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+struct fmc_host {
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+ struct device *dev;
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+ struct mutex *lock;
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+
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+ void __iomem *regbase;
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+ void __iomem *iobase;
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+ struct clk *clk;
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+ void *buffer;
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+ dma_addr_t dma_buffer;
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+
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+ struct spi_nor *nor[FMC_MAX_CHIP_NUM];
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+ struct fmc_priv priv[FMC_MAX_CHIP_NUM];
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+ u32 num_chip;
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+ unsigned int dma_len;
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+};
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+
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+/******************************************************************************/
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+static inline int wait_op_finish(struct fmc_host *host)
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+{
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+ u32 reg;
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+
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+ return readl_poll_timeout(host->regbase + FMC_INT, reg,
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+ (reg & FMC_INT_OP_DONE), 0, FMC_WAIT_TIMEOUT);
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+}
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+
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+static int get_if_type(enum spi_nor_protocol mode)
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+{
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+ enum fmc_iftype if_type;
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+
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+ switch (mode) {
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+ case SNOR_PROTO_1_1_2:
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+ if_type = IF_TYPE_DUAL;
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+ break;
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+ case SNOR_PROTO_1_2_2:
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+ if_type = IF_TYPE_DIO;
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+ break;
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+ case SNOR_PROTO_1_1_4:
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+ if_type = IF_TYPE_QUAD;
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+ break;
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+ case SNOR_PROTO_1_4_4:
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+ if_type = IF_TYPE_QIO;
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+ break;
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+ case SNOR_PROTO_1_1_1:
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+ default:
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+ if_type = IF_TYPE_STD;
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+ break;
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+ }
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+
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+ return if_type;
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+}
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+
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+/******************************************************************************/
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+static void spi_nor_switch_spi_type(struct fmc_host *host)
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+{
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+ unsigned int reg;
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+
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+ reg = fmc_readl(host, FMC_CFG);
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+ reg &= ~FLASH_TYPE_SEL_MASK;
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+ reg |= FMC_CFG_FLASH_SEL(0);
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+ fmc_writel(host, FMC_CFG, reg);
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+}
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+
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+/******************************************************************************/
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+static void bsp_spi_nor_init(struct fmc_host *host)
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+{
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+ unsigned int reg;
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+
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+ /* switch the flash type to spi nor */
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+ spi_nor_switch_spi_type(host);
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+
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+ /* set the boot mode to normal */
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+ reg = fmc_readl(host, FMC_CFG);
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+ if ((reg & FMC_CFG_OP_MODE_MASK) == FMC_CFG_OP_MODE_BOOT) {
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+ reg |= FMC_CFG_OP_MODE(FMC_CFG_OP_MODE_NORMAL);
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+ fmc_writel(host, FMC_CFG, reg);
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+ }
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+
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+ /* hold on STR mode */
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+ reg = fmc_readl(host, FMC_GLOBAL_CFG);
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+ reg &= (~FMC_GLOBAL_CFG_DTR_MODE);
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+ fmc_writel(host, FMC_GLOBAL_CFG, reg);
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+
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+ /* set timming */
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+ reg = TIMING_CFG_TCSH(CS_HOLD_TIME)
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+ | TIMING_CFG_TCSS(CS_SETUP_TIME)
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+ | TIMING_CFG_TSHSL(CS_DESELECT_TIME);
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+ fmc_writel(host, FMC_SPI_TIMING_CFG, reg);
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+}
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+
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+/******************************************************************************/
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+static int bsp_spi_nor_prep(struct spi_nor *nor, enum spi_nor_ops ops)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+ u32 clkrate;
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+ int ret;
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+
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+ mutex_lock(&fmc_switch_mutex);
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+ mutex_lock(host->lock);
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+
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+ clkrate = min_t(u32, priv->clkrate, nor->clkrate);
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+ ret = clk_set_rate(host->clk, clkrate);
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+ if (ret)
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+ goto out;
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+
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+ ret = clk_prepare_enable(host->clk);
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+ if (ret)
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+ goto out;
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+
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+ spi_nor_switch_spi_type(host);
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+
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+ return 0;
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+
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+out:
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+ mutex_unlock(host->lock);
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+ return ret;
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+}
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+
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+/******************************************************************************/
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+static void bsp_spi_nor_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+
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+ clk_disable_unprepare(host->clk);
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+ mutex_unlock(host->lock);
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+ mutex_unlock(&fmc_switch_mutex);
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+}
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+
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+/******************************************************************************/
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+static int bsp_spi_nor_op_reg(struct spi_nor *nor,
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+ u8 opcode, u32 len, u8 optype)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+ u32 reg;
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+
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+ reg = FMC_CMD_CMD1(opcode);
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+ fmc_writel(host, FMC_CMD, reg);
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+
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+ reg = FMC_DATA_NUM_CNT(len);
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+ fmc_writel(host, FMC_DATA_NUM, reg);
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+
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+ reg = OP_CFG_FM_CS(priv->chipselect) | OP_CFG_OEN_EN;
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+ fmc_writel(host, FMC_OP_CFG, reg);
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+
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+ fmc_writel(host, FMC_INT_CLR, 0xff);
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+ reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START | optype;
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+ fmc_writel(host, FMC_OP, reg);
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+
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+ return wait_op_finish(host);
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+}
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+
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+/******************************************************************************/
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+static int bsp_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
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+ int len)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+ int ret;
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+
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+ ret = bsp_spi_nor_op_reg(nor, opcode, len, FMC_OP_READ_DATA_EN);
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+ if (ret)
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+ return ret;
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+
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+ memcpy_fromio(buf, host->iobase, len);
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+ return 0;
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+}
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+
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+/******************************************************************************/
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+static int bsp_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
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+ u8 *buf, int len)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+
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+ if (len)
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+ memcpy_toio(host->iobase, buf, len);
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+
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+ return bsp_spi_nor_op_reg(nor, opcode, len, FMC_OP_WRITE_DATA_EN);
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+}
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+
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+/******************************************************************************/
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+static int bsp_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
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+ dma_addr_t dma_buf, size_t len, u8 op_type)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+ u8 if_type = 0, dummy = 0;
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+ u32 reg;
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+
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+ reg = fmc_readl(host, FMC_CFG);
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+ reg &= ~(FMC_CFG_OP_MODE_MASK | SPI_NOR_ADDR_MODE_MASK);
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+ reg |= FMC_CFG_OP_MODE_NORMAL;
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+ reg |= (nor->addr_width == 4) ? SPI_NOR_ADDR_MODE_4BYTES
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+ : SPI_NOR_ADDR_MODE_3BYTES;
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+ fmc_writel(host, FMC_CFG, reg);
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+
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+ fmc_writel(host, FMC_ADDRL, start_off);
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+
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+ reg = (unsigned int)dma_buf;
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+ fmc_writel(host, FMC_DMA_SADDR_D0, reg);
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+
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+#ifdef CONFIG_64BIT
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+ reg = (dma_buf & FMC_DMA_SADDRH_MASK) >> 32;
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+ fmc_writel(host, FMC_DMA_SADDRH_D0, reg);
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+#endif
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+
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+ fmc_writel(host, FMC_DMA_LEN, FMC_DMA_LEN_SET(len));
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+
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+ reg = OP_CFG_FM_CS(priv->chipselect);
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+ if (op_type == FMC_OP_READ) {
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+ if_type = get_if_type(nor->read_proto);
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+ dummy = nor->read_dummy >> 3;
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+ } else {
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+ if_type = get_if_type(nor->write_proto);
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+ }
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+ reg |= OP_CFG_MEM_IF_TYPE(if_type)
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+ | OP_CFG_DUMMY_NUM(dummy)
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+ | OP_CFG_OEN_EN;
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+ fmc_writel(host, FMC_OP_CFG, reg);
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+
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+ fmc_writel(host, FMC_INT_CLR, 0xff);
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+ reg = OP_CTRL_RW_OP(op_type) | OP_CTRL_DMA_OP_READY;
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+ reg |= (op_type == FMC_OP_READ)
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+ ? OP_CTRL_RD_OPCODE(nor->read_opcode)
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+ : OP_CTRL_WR_OPCODE(nor->program_opcode);
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+ fmc_writel(host, FMC_OP_DMA, reg);
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+
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+ return wait_op_finish(host);
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+}
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+
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+static ssize_t bsp_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
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+ u_char *read_buf)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+ size_t offset;
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+ int ret;
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+
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+ for (offset = 0; offset < len; offset += host->dma_len) {
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+ size_t trans = min_t(size_t, host->dma_len, len - offset);
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+
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+ ret = bsp_spi_nor_dma_transfer(nor,
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+ from + offset, host->dma_buffer, trans, FMC_OP_READ);
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+ if (ret) {
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+ dev_warn(nor->dev, "DMA read timeout\n");
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+ return ret;
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+ }
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+ memcpy(read_buf + offset, host->buffer, trans);
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+ }
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+
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+ return len;
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+}
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+
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+static ssize_t bsp_spi_nor_write(struct spi_nor *nor, loff_t to,
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+ size_t len, const u_char *write_buf)
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+{
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+ struct fmc_priv *priv = nor->priv;
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+ struct fmc_host *host = priv->host;
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+ size_t offset;
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+ int ret;
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+
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+ for (offset = 0; offset < len; offset += host->dma_len) {
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+ size_t trans = min_t(size_t, host->dma_len, len - offset);
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+
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+ memcpy(host->buffer, write_buf + offset, trans);
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+ ret = bsp_spi_nor_dma_transfer(nor,
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+ to + offset, host->dma_buffer, trans, FMC_OP_WRITE);
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+ if (ret) {
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+ dev_warn(nor->dev, "DMA write timeout\n");
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+ return ret;
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+ }
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+ }
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+
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+ return len;
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+}
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+
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+/**
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+ * parse partitions info and register spi flash device as mtd device.
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+ */
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+static int bsp_snor_device_register(struct mtd_info *mtd)
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+{
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+ int ret;
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+ struct mtd_partitions parsed;
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+
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+ /*
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+ * We do not add the whole spi flash as a mtdblock device,
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+ * To avoid the number of nand partition +1.
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+ */
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+ memset(&parsed, 0, sizeof(parsed));
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+ ret = parse_mtd_partitions(mtd, NULL, &parsed, NULL);
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+ if (ret)
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+ return ret;
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+
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+ return parsed.nr_parts ? mtd_device_register(mtd, NULL, 0) : parsed.nr_parts;
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+}
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+
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+/**
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+ * Get spi flash device information and register it as a mtd device.
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+ */
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+static int bsp_spi_nor_register(struct device_node *np,
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+ struct fmc_host *host)
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+{
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+ struct device *dev = host->dev;
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+ struct spi_nor *nor;
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+ struct fmc_priv *priv = &host->priv[host->num_chip];
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+ struct mtd_info *mtd;
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+ int ret;
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+ struct spi_nor_modes modes = {
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+ .rd_modes = SNOR_MODE_SLOW,
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+ .wr_modes = SNOR_MODE_1_1_1,
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+ };
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+
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+ nor = devm_kzalloc(dev, sizeof(*nor), GFP_KERNEL);
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+ if (!nor)
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+ return -ENOMEM;
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+
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+ nor->dev = dev;
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+ spi_nor_set_flash_node(nor, np);
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ ret = of_property_read_u32(np, "reg", &priv->chipselect);
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+ if (ret) {
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+ dev_err(dev, "There's no reg property for %s\n",
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+ np->full_name);
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+ return ret;
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+ }
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+
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+ if (priv->chipselect != host->num_chip) {
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+ dev_warn(dev, " The CS: %d states in device trees isn't real " \
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+ "chipselect on board\n, using CS: %d instead. ",
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+ priv->chipselect, host->num_chip);
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+ priv->chipselect = host->num_chip;
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+ }
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+
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+ ret = of_property_read_u32(np, "spi-max-frequency",
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+ &priv->clkrate);
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+ if (ret) {
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+ dev_err(dev, "There's no spi-max-frequency property for %s\n",
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+ np->full_name);
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+ return ret;
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+ }
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+ priv->host = host;
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+ nor->priv = priv;
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+
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+ nor->prepare = bsp_spi_nor_prep;
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+ nor->unprepare = bsp_spi_nor_unprep;
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+ nor->read_reg = bsp_spi_nor_read_reg;
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+ nor->write_reg = bsp_spi_nor_write_reg;
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+ nor->read = bsp_spi_nor_read;
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+ nor->write = bsp_spi_nor_write;
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+
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+ modes.rd_modes |= SNOR_MODE_1_1_1
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+ | SNOR_MODE_1_1_2
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+ | SNOR_MODE_1_2_2;
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+#ifndef CONFIG_CLOSE_SPI_8PIN_4IO
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+ modes.rd_modes |= SNOR_MODE_1_1_4 | SNOR_MODE_1_4_4;
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+ modes.wr_modes |= SNOR_MODE_1_1_4 | SNOR_MODE_1_4_4;
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+#endif
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+ ret = spi_nor_scan(nor, NULL, &modes);
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+ if (ret)
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+ return ret;
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+
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+ mtd = &nor->mtd;
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+ mtd->name = np->name;
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+ ret = bsp_snor_device_register(mtd);
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+ if (ret)
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+ return ret;
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+
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+ /* current chipselect has scanned, to detect next chipselect */
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+ fmc_cs_user[host->num_chip]++;
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+ host->nor[host->num_chip] = nor;
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+ return 0;
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+}
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+
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+static void bsp_spi_nor_unregister_all(struct fmc_host *host)
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+{
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+ int i;
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+
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+ for (i = 0; i < host->num_chip; i++)
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+ mtd_device_unregister(&host->nor[i]->mtd);
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+}
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+
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+static int bsp_spi_nor_register_all(struct fmc_host *host)
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+{
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+ struct device *dev = host->dev;
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+ struct device_node *np = NULL;
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+ int ret;
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+
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+ for_each_available_child_of_node(dev->of_node, np) {
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+ if (fmc_cs_user[host->num_chip]) {
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+ dev_warn(dev, "Current CS(%d) is occupied.\n",
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+ host->num_chip);
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+ continue;
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+ }
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+ ret = bsp_spi_nor_register(np, host);
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+ if (ret)
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+ goto fail;
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+
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+ if (host->num_chip == FMC_MAX_CHIP_NUM) {
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+ dev_warn(dev, "Flash device number exceeds the "
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+ "maximum chipselect number\n");
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+ break;
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+ }
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+
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+ host->num_chip++;
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+
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+ }
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+
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+ return 0;
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+
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+fail:
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+ bsp_spi_nor_unregister_all(host);
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+ return ret;
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+}
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+
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+/******************************************************************************/
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+static int bsp_spi_nor_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct bsp_fmc *fmc = dev_get_drvdata(dev->parent);
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+ struct fmc_host *host;
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+ int ret;
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+
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+ if (!fmc) {
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+ dev_err(&pdev->dev, "get mfd fmc devices failed\n");
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+ return -ENXIO;
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+ }
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+
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+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
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+ if (!host)
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+ return -ENOMEM;
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+
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+ platform_set_drvdata(pdev, host);
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+ host->dev = dev;
|
|
+
|
|
+ host->regbase = fmc->regbase;
|
|
+ host->iobase = fmc->iobase;
|
|
+ host->clk = fmc->clk;
|
|
+ host->lock = &fmc->lock;
|
|
+ host->buffer = fmc->buffer;
|
|
+ host->dma_buffer = fmc->dma_buffer;
|
|
+ host->dma_len = fmc->dma_len;
|
|
+
|
|
+ clk_prepare_enable(host->clk);
|
|
+ bsp_spi_nor_init(host);
|
|
+ ret = bsp_spi_nor_register_all(host);
|
|
+ if (ret)
|
|
+ dev_warn(dev, "spi nor register fail!\n");
|
|
+
|
|
+ clk_disable_unprepare(host->clk);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+/******************************************************************************/
|
|
+static int bsp_spi_nor_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct fmc_host *host = platform_get_drvdata(pdev);
|
|
+ if (host == NULL){
|
|
+ dev_err(&pdev->dev, "host is NULL ,remove err !!\n");
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ bsp_spi_nor_unregister_all(host);
|
|
+ clk_disable_unprepare(host->clk);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/******************************************************************************/
|
|
+static void bsp_spi_nor_driver_shutdown(struct platform_device *pdev)
|
|
+{
|
|
+ int i;
|
|
+ struct fmc_host *host = platform_get_drvdata(pdev);
|
|
+
|
|
+ if (!host)
|
|
+ return;
|
|
+
|
|
+ mutex_lock(host->lock);
|
|
+ clk_prepare_enable(host->clk);
|
|
+
|
|
+ spi_nor_switch_spi_type(host);
|
|
+ for (i = 0; i < host->num_chip; i++)
|
|
+ spi_nor_driver_shutdown(host->nor[i]);
|
|
+
|
|
+ clk_disable_unprepare(host->clk);
|
|
+ mutex_unlock(host->lock);
|
|
+ dev_dbg(host->dev, "End of driver shutdown\n");
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+/******************************************************************************/
|
|
+static int bsp_spi_nor_driver_suspend(struct platform_device *pdev,
|
|
+ pm_message_t state)
|
|
+{
|
|
+ int i;
|
|
+ struct fmc_host *host = platform_get_drvdata(pdev);
|
|
+
|
|
+ if (!host)
|
|
+ return 0;
|
|
+
|
|
+ mutex_lock(host->lock);
|
|
+ clk_prepare_enable(host->clk);
|
|
+
|
|
+ spi_nor_switch_spi_type(host);
|
|
+ for (i = 0; i < host->num_chip; i++)
|
|
+ spi_nor_suspend(host->nor[i], state);
|
|
+
|
|
+ clk_disable_unprepare(host->clk);
|
|
+ mutex_unlock(host->lock);
|
|
+ dev_dbg(host->dev, "End of suspend\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/******************************************************************************/
|
|
+static int bsp_spi_nor_driver_resume(struct platform_device *pdev)
|
|
+{
|
|
+ int i;
|
|
+ struct fmc_host *host = platform_get_drvdata(pdev);
|
|
+
|
|
+ if (!host)
|
|
+ return 0;
|
|
+
|
|
+ mutex_lock(host->lock);
|
|
+ clk_prepare_enable(host->clk);
|
|
+
|
|
+ spi_nor_switch_spi_type(host);
|
|
+ for (i = 0; i < host->num_chip; i++)
|
|
+ spi_nor_resume(host->nor[i]);
|
|
+
|
|
+ mutex_unlock(host->lock);
|
|
+ dev_dbg(host->dev, "End of resume\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#endif /* End of CONFIG_PM */
|
|
+
|
|
+/******************************************************************************/
|
|
+static const struct of_device_id bsp_spi_nor_dt_ids[] = {
|
|
+ { .compatible = "goke,fmc-spi-nor"},
|
|
+ { /* sentinel */ }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, bsp_spi_nor_dt_ids);
|
|
+
|
|
+/******************************************************************************/
|
|
+static struct platform_driver bsp_spi_nor_driver = {
|
|
+ .driver = {
|
|
+ .name = "bsp-sfc",
|
|
+ .of_match_table = bsp_spi_nor_dt_ids,
|
|
+ },
|
|
+ .probe = bsp_spi_nor_probe,
|
|
+ .remove = bsp_spi_nor_remove,
|
|
+ .shutdown = bsp_spi_nor_driver_shutdown,
|
|
+#ifdef CONFIG_PM
|
|
+ .suspend = bsp_spi_nor_driver_suspend,
|
|
+ .resume = bsp_spi_nor_driver_resume,
|
|
+#endif
|
|
+};
|
|
+module_platform_driver(bsp_spi_nor_driver);
|
|
+
|
|
+MODULE_LICENSE("GPL v2");
|
|
+MODULE_DESCRIPTION("Goke SPI Nor Flash Controller Driver");
|