mirror of https://github.com/OpenIPC/firmware.git
250 lines
7.0 KiB
Diff
250 lines
7.0 KiB
Diff
--- linux-4.9.37/drivers/mtd/nand/gkfmc100/fmc100_spi_general.c 1970-01-01 03:00:00.000000000 +0300
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+++ linux-4.9.y/drivers/mtd/nand/gkfmc100/fmc100_spi_general.c 2021-06-07 13:01:33.000000000 +0300
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@@ -0,0 +1,246 @@
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+/*
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+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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+ */
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+
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+/*
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+ Send set/get features command to SPI Nand flash
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+*/
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+u_char spi_nand_feature_op(struct fmc_spi *spi, u_char op, u_char addr,
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+ u_char val)
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+{
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+ unsigned int reg;
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+ const char *str[] = {"Get", "Set"};
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+ struct fmc_host *host = (struct fmc_host *)spi->host;
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+
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+ if ((op == GET_OP) && (STATUS_ADDR == addr)) {
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+ if (SR_DBG) {
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+ pr_info("\n");
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+ }
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+ FMC_PR(SR_DBG, "\t\t|*-Start Get Status\n");
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+
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+ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
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+ fmc_writel(host, FMC_OP_CFG, reg);
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+ FMC_PR(SR_DBG, "\t\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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+
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+ reg = FMC_OP_READ_STATUS_EN | FMC_OP_REG_OP_START;
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+ fmc_writel(host, FMC_OP, reg);
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+ FMC_PR(SR_DBG, "\t\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
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+
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+ FMC_CMD_WAIT_CPU_FINISH(host);
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+
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+ val = fmc_readl(host, FMC_STATUS);
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+ FMC_PR(SR_DBG, "\t\t|*-End Get Status, result: %#x\n", val);
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+
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+ return val;
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+ }
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+
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+ FMC_PR(FT_DBG, "\t|||*-Start %s feature, addr[%#x]\n", str[op], addr);
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+
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+ fmc100_ecc0_switch(host, ENABLE);
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+
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+ reg = FMC_CMD_CMD1(op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES);
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+ fmc_writel(host, FMC_CMD, reg);
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+ FMC_PR(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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+
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+ fmc_writel(host, FMC_ADDRL, addr);
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+ FMC_PR(FT_DBG, "\t||||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, addr);
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+
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+ reg = OP_CFG_FM_CS(host->cmd_op.cs)
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+ | OP_CFG_ADDR_NUM(FEATURES_OP_ADDR_NUM)
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+ | OP_CFG_OEN_EN;
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+ fmc_writel(host, FMC_OP_CFG, reg);
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+ FMC_PR(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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+
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+ reg = FMC_DATA_NUM_CNT(FEATURES_DATA_LEN);
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+ fmc_writel(host, FMC_DATA_NUM, reg);
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+ FMC_PR(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
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+
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+ reg = FMC_OP_CMD1_EN
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+ | FMC_OP_ADDR_EN
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+ | FMC_OP_REG_OP_START;
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+
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+ if (op == SET_OP) {
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+ reg |= FMC_OP_WRITE_DATA_EN;
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+ fmc_writeb(val, host->iobase);
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+ FMC_PR(FT_DBG, "\t||||-Write IO[%#lx]%#x\n", (long)host->iobase,
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+ *(u_char *)host->iobase);
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+ } else {
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+ reg |= FMC_OP_READ_DATA_EN;
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+ }
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+
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+ fmc_writel(host, FMC_OP, reg);
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+ FMC_PR(FT_DBG, "\t||||-Set OP[%#x]%#x\n", FMC_OP, reg);
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+
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+ FMC_CMD_WAIT_CPU_FINISH(host);
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+
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+ if (op == GET_OP) {
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+ val = fmc_readb(host->iobase);
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+ FMC_PR(FT_DBG, "\t||||-Read IO[%#lx]%#x\n", (long)host->iobase,
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+ *(u_char *)host->iobase);
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+ }
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+
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+ fmc100_ecc0_switch(host, DISABLE);
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+
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+ FMC_PR(FT_DBG, "\t|||*-End %s Feature[%#x]:%#x\n", str[op], addr, val);
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+
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+ return val;
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+}
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+
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+/*****************************************************************************/
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+/*
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+ Read status[C0H]:[0]bit OIP, judge whether the device is busy or not
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+*/
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+static int spi_general_wait_ready(struct fmc_spi *spi)
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+{
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+ unsigned char status;
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+ unsigned long deadline = jiffies + FMC_MAX_READY_WAIT_JIFFIES;
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+ struct fmc_host *host = (struct fmc_host *)spi->host;
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+
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+ do {
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+ status = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
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+ if (!(status & STATUS_OIP_MASK)) {
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+ if ((host->cmd_op.l_cmd == NAND_CMD_ERASE2)
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+ && (status & STATUS_E_FAIL_MASK)) {
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+ return status;
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+ }
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+ if ((host->cmd_op.l_cmd == NAND_CMD_PAGEPROG)
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+ && (status & STATUS_P_FAIL_MASK)) {
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+ return status;
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+ }
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+ return 0;
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+ }
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+
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+ cond_resched();
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+
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+ } while (!time_after_eq(jiffies, deadline));
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+
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+ DB_MSG("Error: SPI Nand wait ready timeout, status: %#x\n", status);
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+
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+ return 1;
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+}
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+
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+/*****************************************************************************/
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+/*
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+ Send write enable cmd to SPI Nand, status[C0H]:[2]bit WEL must be set 1
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+*/
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+static int spi_general_write_enable(struct fmc_spi *spi)
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+{
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+ unsigned int reg;
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+ struct fmc_host *host = (struct fmc_host *)spi->host;
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+
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+ if (WE_DBG) {
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+ pr_info("\n");
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+ }
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+ FMC_PR(WE_DBG, "\t|*-Start Write Enable\n");
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+
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+ reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
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+ if (reg & STATUS_WEL_MASK) {
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+ FMC_PR(WE_DBG, "\t||-Write Enable was opened! reg: %#x\n",
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+ reg);
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+ return 0;
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+ }
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+
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+ reg = fmc_readl(host, FMC_GLOBAL_CFG);
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+ FMC_PR(WE_DBG, "\t||-Get GLOBAL_CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
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+ if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
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+ reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
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+ fmc_writel(host, FMC_GLOBAL_CFG, reg);
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+ FMC_PR(WE_DBG, "\t||-Set GLOBAL_CFG[%#x]%#x\n",
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+ FMC_GLOBAL_CFG, reg);
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+ }
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+
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+ reg = FMC_CMD_CMD1(SPI_CMD_WREN);
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+ fmc_writel(host, FMC_CMD, reg);
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+ FMC_PR(WE_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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+
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+ reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
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+ fmc_writel(host, FMC_OP_CFG, reg);
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+ FMC_PR(WE_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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+
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+ reg = FMC_OP_CMD1_EN | FMC_OP_REG_OP_START;
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+ fmc_writel(host, FMC_OP, reg);
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+ FMC_PR(WE_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
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+
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+ FMC_CMD_WAIT_CPU_FINISH(host);
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+
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+#if WE_DBG
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+ spi->driver->wait_ready(spi);
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+
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+ reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
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+ if (reg & STATUS_WEL_MASK) {
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+ FMC_PR(WE_DBG, "\t||-Write Enable success. reg: %#x\n", reg);
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+ } else {
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+ DB_MSG("Error: Write Enable failed! reg: %#x\n", reg);
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+ return reg;
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+ }
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+#endif
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+
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+ FMC_PR(WE_DBG, "\t|*-End Write Enable\n");
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+ return 0;
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+}
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+
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+/*****************************************************************************/
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+/*
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+ judge whether SPI Nand support QUAD read/write or not
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+*/
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+static int spi_is_quad(struct fmc_spi *spi)
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+{
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+ const char *if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
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+
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+ FMC_PR(QE_DBG, "\t\t|||*-SPI read iftype: %s write iftype: %s\n",
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+ if_str[spi->read->iftype], if_str[spi->write->iftype]);
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+
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+ if ((spi->read->iftype == IF_TYPE_QUAD)
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+ || (spi->read->iftype == IF_TYPE_QIO)
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+ || (spi->write->iftype == IF_TYPE_QUAD)
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+ || (spi->write->iftype == IF_TYPE_QIO)) {
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+ return 1;
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+ }
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+
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+ return 0;
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+}
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+
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+/*****************************************************************************/
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+/*
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+ Send set features cmd to SPI Nand, feature[B0H]:[0]bit QE would be set
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+*/
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+static int spi_general_qe_enable(struct fmc_spi *spi)
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+{
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+ unsigned int reg, op;
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+ const char *str[] = {"Disable", "Enable"};
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+
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+ FMC_PR(QE_DBG, "\t||*-Start SPI Nand flash QE\n");
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+
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+ op = spi_is_quad(spi);
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+
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+ FMC_PR(QE_DBG, "\t|||*-End Quad check, SPI Nand %s Quad.\n", str[op]);
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+
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+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
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+ FMC_PR(QE_DBG, "\t|||-Get [%#x]feature: %#x\n", FEATURE_ADDR, reg);
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+ if ((reg & FEATURE_QE_ENABLE) == op) {
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+ FMC_PR(QE_DBG, "\t||*-SPI Nand quad was %sd!\n", str[op]);
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+ return op;
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+ }
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+
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+ if (op == ENABLE) {
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+ reg |= FEATURE_QE_ENABLE;
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+ } else {
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+ reg &= ~FEATURE_QE_ENABLE;
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+ }
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+
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+ spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
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+ FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad\n", str[op]);
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+
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+ spi->driver->wait_ready(spi);
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+
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+ reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
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+ if ((reg & FEATURE_QE_ENABLE) == op) {
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+ FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad succeed!\n", str[op]);
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+ } else {
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+ DB_MSG("Error: %s Quad failed! reg: %#x\n", str[op], reg);
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+ }
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+
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+ FMC_PR(QE_DBG, "\t||*-End SPI Nand %s Quad.\n", str[op]);
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+
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+ return op;
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+}
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