mirror of https://github.com/OpenIPC/firmware.git
136 lines
4.2 KiB
Diff
136 lines
4.2 KiB
Diff
--- linux-4.9.37/drivers/dma/edmac_goke.h 1970-01-01 03:00:00.000000000 +0300
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+++ linux-4.9.y/drivers/dma/edmac_goke.h 2021-06-07 13:01:33.000000000 +0300
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@@ -0,0 +1,132 @@
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+/*
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+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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+ */
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+
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+#ifndef __EDMAC_H__
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+#define __EDMAC_H__
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+
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+/* debug control */
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+extern int edmac_trace_level;
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+#define EDMAC_TRACE_LEVEL 5
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+
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+#define EDMAC_TRACE_FMT KERN_INFO
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+
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+//#define DEBUG_EDMAC
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+#ifdef DEBUG_EDMAC
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+
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+#define edmac_trace(level, msg...) do { \
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+ if ((level) >= edmac_trace_level) { \
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+ printk(EDMAC_TRACE_FMT"%s:%d: ", __func__, __LINE__); \
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+ printk(msg); \
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+ printk("\n"); \
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+ } \
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+} while (0)
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+
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+
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+#define edmac_assert(cond) do { \
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+ if (!(cond)) { \
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+ printk(KERN_ERR "Assert:edmac:%s:%d\n", \
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+ __func__, \
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+ __LINE__); \
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+ BUG(); \
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+ } \
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+} while (0)
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+
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+#define edmac_error(s...) do { \
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+ printk(KERN_ERR "edmac:%s:%d: ", __func__, __LINE__); \
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+ printk(s); \
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+ printk("\n"); \
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+} while (0)
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+
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+#else
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+
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+#define edmac_trace(level, msg...) do { } while (0)
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+#define edmac_assert(level, msg...) do { } while (0)
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+#define edmac_error(level, msg...) do { } while (0)
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+
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+#endif
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+
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+#define edmac_readl(addr) ({ unsigned int reg = readl((void *)(addr)); \
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+ reg; })
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+
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+#define edmac_writel(v, addr) do { writel(v, (void *)(addr)); \
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+} while (0)
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+
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+
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+#define MAX_TRANSFER_BYTES 0xffff
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+
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+/* reg offset */
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+#define EDMAC_INT_STAT (0x0)
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+#define EDMAC_INT_TC1 (0x4)
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+#define EDMAC_INT_TC2 (0x8)
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+#define EDMAC_INT_ERR1 (0xc)
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+#define EDMAC_INT_ERR2 (0x10)
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+#define EDMAC_INT_ERR3 (0x14)
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+
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+#define EDMAC_INT_TC1_MASK (0x18)
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+#define EDMAC_INT_TC2_MASK (0x1c)
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+#define EDMAC_INT_ERR1_MASK (0x20)
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+#define EDMAC_INT_ERR2_MASK (0x24)
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+#define EDMAC_INT_ERR3_MASK (0x28)
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+
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+#define EDMAC_INT_TC1_RAW (0x600)
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+#define EDMAC_INT_TC2_RAW (0x608)
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+#define EDMAC_INT_ERR1_RAW (0x610)
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+#define EDMAC_INT_ERR2_RAW (0x618)
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+#define EDMAC_INT_ERR3_RAW (0x620)
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+
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+#define EDMAC_Cx_CURR_CNT0(cn) (0x404+cn*0x20)
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+#define EDMAC_Cx_CURR_SRC_ADDR_L(cn) (0x408+cn*0x20)
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+#define EDMAC_Cx_CURR_SRC_ADDR_H(cn) (0x40c+cn*0x20)
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+#define EDMAC_Cx_CURR_DEST_ADDR_L(cn) (0x410+cn*0x20)
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+#define EDMAC_Cx_CURR_DEST_ADDR_H(cn) (0x414+cn*0x20)
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+
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+#define EDMAC_CH_PRI (0x688)
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+#define EDMAC_CH_STAT (0x690)
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+#define EDMAC_DMA_CTRL (0x698)
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+
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+#define EDMAC_Cx_BASE(cn) (0x800+cn*0x40)
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+#define EDMAC_Cx_LLI_L(cn) (0x800+cn*0x40)
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+#define EDMAC_Cx_LLI_H(cn) (0x804+cn*0x40)
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+#define EDMAC_Cx_CNT0(cn) (0x81c+cn*0x40)
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+#define EDMAC_Cx_SRC_ADDR_L(cn) (0x820+cn*0x40)
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+#define EDMAC_Cx_SRC_ADDR_H(cn) (0x824+cn*0x40)
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+#define EDMAC_Cx_DEST_ADDR_L(cn) (0x828+cn*0x40)
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+#define EDMAC_Cx_DEST_ADDR_H(cn) (0x82c+cn*0x40)
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+#define EDMAC_Cx_CONFIG(cn) (0x830+cn*0x40)
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+
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+#define EDMAC_ALL_CHAN_CLR (0xff)
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+#define EDMAC_INT_ENABLE_ALL_CHAN (0xff)
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+
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+
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+#define EDMAC_CONFIG_SRC_INC (1<<31)
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+#define EDMAC_CONFIG_DST_INC (1<<30)
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+
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+#define EDMAC_CONFIG_SRC_WIDTH_SHIFT (16)
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+#define EDMAC_CONFIG_DST_WIDTH_SHIFT (12)
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+#define EDMAC_WIDTH_8BIT (0x0)
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+#define EDMAC_WIDTH_16BIT (0x1)
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+#define EDMAC_WIDTH_32BIT (0x10)
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+#define EDMAC_WIDTH_64BIT (0x11)
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+
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+#define EDMAC_MAX_BURST_WIDTH (16)
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+#define EDMAC_MIN_BURST_WIDTH (1)
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+#define EDMAC_CONFIG_SRC_BURST_SHIFT (24)
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+#define EDMAC_CONFIG_DST_BURST_SHIFT (20)
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+
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+#define EDMAC_LLI_ALIGN 0x40
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+#define EDMAC_LLI_DISABLE 0x0
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+#define EDMAC_LLI_ENABLE 0x2
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+
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+#define EDMAC_CXCONFIG_SIGNAL_SHIFT (0x4)
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+#define EDMAC_CXCONFIG_MEM_TYPE (0x0)
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+#define EDMAC_CXCONFIG_DEV_MEM_TYPE (0x1)
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+#define EDMAC_CXCONFIG_TSF_TYPE_SHIFT (0x2)
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+#define EDMAC_CxCONFIG_LLI_START (0x1)
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+
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+#define EDMAC_CXCONFIG_ITC_EN (0x1)
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+#define EDMAC_CXCONFIG_ITC_EN_SHIFT (0x1)
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+
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+#define CCFG_EN 0x1
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+
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+#endif
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