mirror of https://github.com/OpenIPC/firmware.git
117 lines
2.8 KiB
Diff
117 lines
2.8 KiB
Diff
--- linux-4.9.37/drivers/clk/goke/reset.c 1970-01-01 03:00:00.000000000 +0300
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+++ linux-4.9.y/drivers/clk/goke/reset.c 2021-06-07 13:01:33.000000000 +0300
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@@ -0,0 +1,113 @@
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+/*
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+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/of_address.h>
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+#include <linux/platform_device.h>
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+#include <linux/reset-controller.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+#include "reset.h"
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+
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+#define GOKE_RESET_BIT_MASK 0x1f
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+#define GOKE_RESET_OFFSET_SHIFT 8
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+#define GOKE_RESET_OFFSET_MASK 0xffff00
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+
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+struct gk_reset_controller {
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+ spinlock_t lock;
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+ void __iomem *membase;
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+ struct reset_controller_dev rcdev;
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+};
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+
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+
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+#define to_gk_reset_controller(rcdev) \
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+ container_of(rcdev, struct gk_reset_controller, rcdev)
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+
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+static int gk_reset_of_xlate(struct reset_controller_dev *rcdev,
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+ const struct of_phandle_args *reset_spec)
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+{
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+ u32 offset;
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+ u8 bit;
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+
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+ offset = (reset_spec->args[0] << GOKE_RESET_OFFSET_SHIFT)
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+ & GOKE_RESET_OFFSET_MASK;
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+ bit = reset_spec->args[1] & GOKE_RESET_BIT_MASK;
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+
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+ return (offset | bit);
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+}
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+
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+static int gk_reset_assert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct gk_reset_controller *rstc = to_gk_reset_controller(rcdev);
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+ unsigned long flags;
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+ u32 offset, reg;
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+ u8 bit;
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+
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+ offset = (id & GOKE_RESET_OFFSET_MASK) >> GOKE_RESET_OFFSET_SHIFT;
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+ bit = id & GOKE_RESET_BIT_MASK;
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+
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+ spin_lock_irqsave(&rstc->lock, flags);
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+
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+ reg = readl(rstc->membase + offset);
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+ writel(reg | BIT(bit), rstc->membase + offset);
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+
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+ spin_unlock_irqrestore(&rstc->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int gk_reset_deassert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct gk_reset_controller *rstc = to_gk_reset_controller(rcdev);
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+ unsigned long flags;
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+ u32 offset, reg;
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+ u8 bit;
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+
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+ offset = (id & GOKE_RESET_OFFSET_MASK) >> GOKE_RESET_OFFSET_SHIFT;
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+ bit = id & GOKE_RESET_BIT_MASK;
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+
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+ spin_lock_irqsave(&rstc->lock, flags);
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+
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+ reg = readl(rstc->membase + offset);
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+ writel(reg & ~BIT(bit), rstc->membase + offset);
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+
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+ spin_unlock_irqrestore(&rstc->lock, flags);
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+
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+ return 0;
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+}
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+
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+static const struct reset_control_ops gk_reset_ops = {
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+ .assert = gk_reset_assert,
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+ .deassert = gk_reset_deassert,
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+};
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+
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+int __init gk_reset_init(struct device_node *np,
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+ int nr_rsts)
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+{
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+ struct gk_reset_controller *rstc;
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+
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+ rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
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+ if (!rstc)
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+ return -ENOMEM;
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+
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+ rstc->membase = of_iomap(np, 0);
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+ if (!rstc->membase){
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+ kfree(rstc);
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+ return -EINVAL;
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+ }
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+
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+ spin_lock_init(&rstc->lock);
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+
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+ rstc->rcdev.owner = THIS_MODULE;
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+ rstc->rcdev.nr_resets = nr_rsts;
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+ rstc->rcdev.ops = &gk_reset_ops;
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+ rstc->rcdev.of_node = np;
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+ rstc->rcdev.of_reset_n_cells = 2;
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+ rstc->rcdev.of_xlate = gk_reset_of_xlate;
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+
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+ return reset_controller_register(&rstc->rcdev);
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+}
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+EXPORT_SYMBOL_GPL(gk_reset_init);
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