firmware/br-ext-chip-allwinner/board/v83x/kernel/patches/00000-sound_soc_sunxi_sunxi-mad.h.patch

diff -drupN a/sound/soc/sunxi/sunxi-mad.h b/sound/soc/sunxi/sunxi-mad.h
--- a/sound/soc/sunxi/sunxi-mad.h	1970-01-01 03:00:00.000000000 +0300
+++ b/sound/soc/sunxi/sunxi-mad.h	2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,348 @@
+/*
+ * sound\soc\sunxi\sunxi_mad.h
+ * (C) Copyright 2018-2023
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Wolfgang <qinzhenying@allwinnertech.com>
+ *
+ * some simple description for this code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __SUNXI_MAD_H
+#define __SUNXI_MAD_H
+
+#include "sunxi-pcm.h"
+
+#undef SUNXI_MAD_DEBUG_INFO
+
+#ifdef CONFIG_ARCH_SUN8IW18
+/* SUN8IW18P1 should not be setup. */
+#undef SUNXI_MAD_NETLINK_USE
+#undef SUNXI_MAD_NETLINK_APP_PAUSE_USE
+#undef SUNXI_MAD_NETLINK_APP_PAUSE_USE
+#undef MAD_CLK_ALWAYS_ON
+//#undef SUNXI_LPSD_CLK_ALWAYS_ON
+#define SUNXI_LPSD_CLK_ALWAYS_ON
+#undef SUNXI_MAD_DATA_INT_USE
+#define SUNXI_MAD_SRAM_SUSPEND_RESET
+#endif
+
+struct sunxi_mad_priv {
+	struct sunxi_mad_info *sunxi_mad;
+	unsigned int mad_bind;
+	/* mad params */
+	unsigned int sample_rate;
+	unsigned int lpsd_chan_sel;
+	unsigned int mad_standby_chan_sel;
+	unsigned int audio_src_chan_num;
+};
+
+enum mad_sram_bmode {
+	MAD_SRAM_BMODE_NORMAL = 0,
+	MAD_SRAM_BMODE_BOOT = 1,
+};
+
+enum mad_path_sel {
+	MAD_PATH_NONE = 0,
+	MAD_PATH_I2S0 = 1,
+	MAD_PATH_CODEC = 2,
+	MAD_PATH_DMIC = 3,
+	MAD_PATH_I2S1 = 4,
+	MAD_PATH_I2S2 = 5,
+};
+
+#ifdef CONFIG_ARCH_SUN8IW18
+#undef SUNXI_MAD_DATA_INT_USE
+#endif
+
+#define	EVT_MAX_SIZE		256
+#define	SUNXI_NETLINK_MAD	30
+
+/*------------------MAD register definition--------------------*/
+#define SUNXI_MAD_CTRL			0x00
+#define SUNXI_MAD_SRAM_POINT		0x04
+#define SUNXI_MAD_SRAM_SIZE		0x08
+#define SUNXI_MAD_SRAM_RD_POINT		0x0C
+#define SUNXI_MAD_RD_SIZE		0x10
+#define SUNXI_MAD_SRAM_STORE_TH		0x14
+#define SUNXI_MAD_SRAM_AHB1_TX_TH	0x18
+#define SUNXI_MAD_SRAM_AHB1_RX_TH	0x1C
+#define SUNXI_MAD_SRAM_WAKE_BACK_DATA	0x20
+#define SUNXI_MAD_AD_PATH_SEL		0x24
+#define SUNXI_MAD_LPSD_AD_SYNC_FC	0x28
+#define SUNXI_MAD_LPSD_TH		0x2C
+#define SUNXI_MAD_LPSD_RRUN		0x30
+#define	SUNXI_MAD_LPSD_RSTOP		0x34
+#define	SUNXI_MAD_LPSD_ECNT		0x38
+#define SUNXI_MAD_SRAM_CH_MASK		0x3C
+#define SUNXI_MAD_LPSD_CH_MASK		0x40
+#define SUNXI_MAD_SRAM_SEC_REGION_REG	0x44
+#define SUNXI_MAD_SRAM_PRE_DSIZE	0x48
+#define SUNXI_MAD_DMA_TF_SIZE		0x4C
+#define SUNXI_MAD_DMA_TF_LAST_SIZE	0x50
+#define	SUNXI_MAD_INT_ST_CLR		0x60
+#define	SUNXI_MAD_INT_MASK		0x64
+#define	SUNXI_MAD_STA			0x68
+#define	SUNXI_MAD_DEBUG			0x6C
+
+/*SUNXI_MAD_CTRL: 0x00*/
+#define AUDIO_DATA_SYNC_FRC		7
+#define SRAM_RST			6
+#define DMA_TYPE			5
+#define DMA_EN				4
+#define CPUS_RD_DONE			3
+#define GO_ON_SLEEP			2
+#define KEY_WORD_OK			1
+#define MAD_EN				0
+/* DMA type*/
+#define DMA_TYPE_MASK			0x1
+#define DMA_TYPE_IO			0x1
+#define DMA_TYPE_MEM			0x0
+
+/*SUNXI_MAD_SRAM_POINT: 0x04*/
+#define MAD_SRAM_PONT			0
+
+/*SUNXI_MAD_SRAM_SIZE: 0x08*/
+#define MAD_SRAM_SIZE			0
+
+/*SUNXI_MAD_SRAM_RD_POINT: 0x0C*/
+#define MAD_SRAM_RD_POINT		0
+
+/*SUNXI_MAD_SRAM_RD_SIZE(unit: half word): 0x10*/
+#define MAD_SRAM_RD_SIZE		0
+
+/*SUNXI_MAD_SRAM_STORE_TH(unit: half word): 0x14*/
+#define MAD_SRAM_STORE_TH		0
+
+/*SUNXI_MAD_SRAM_AHB1_TX_TH(unit: byte): 0x18*/
+#define MAD_SRAM_AHB1_TX_TH		0
+
+/*SUNXI_MAD_SRAM_AHB1_RX_TH(unit: byte): 0x1C*/
+#define MAD_SRAM_AHB1_RX_TH		0
+
+/*SUNXI_MAD_SRAM_WAKE_BACK_DATA(unit: frame): 0x20*/
+#define MAD_SRAM_WAKE_BACK_DATA		0
+
+/*SUNXI_MAD_AD_PATH_SEL: 0x24*/
+#define MAD_AD_PATH_SEL			0
+#define MAD_AD_PATH_SEL_MASK		0xF
+/*MAD audio src sel*/
+#define MAD_AD_PATH_NO_SRC		0x0
+#define MAD_AD_PATH_I2S0_SRC		0x1
+#define MAD_AD_PATH_CODEC_SRC		0x2
+#define MAD_AD_PATH_DMIC_SRC		0x3
+#define MAD_AD_PATH_I2S1_SRC		0x4
+#define MAD_AD_PATH_I2S2_SRC		0x5
+
+/*SUNXI_MAD_LPSD_AD_SYNC_FC: 0x28*/
+#define MAD_LPSD_AD_SYNC_FC		0
+#define MAD_LPSD_AD_SYNC_FC_DEF		0X20
+
+/*SUNXI_MAD_LPSD_TH: 0x2C*/
+#define MAD_LPSD_TH			0
+
+/*SUNXI_MAD_LPSD_RRUN: 0x30*/
+#define MAD_LPSD_RRUN			0
+
+/*SUNXI_MAD_LPSD_RSTOP: 0x34*/
+#define MAD_LPSD_RSTOP			0
+
+/*SUNXI_MAD_LPSD_ECNT: 0x38*/
+#define MAD_LPSD_ECNT			0
+
+/*SUNXI_MAD_SRAM_CH_MASK: 0x3C*/
+#define MAD_CH_CHANGE_EN		30
+#define MAD_CH_COM_NUM			26
+#define MAD_AD_SRC_CH_NUM		21
+#define MAD_SRAM_CH_NUM			16
+#define MAD_SRAM_CH_MASK		0
+
+#define MAD_SRAM_CH_NUM_MASK    0x1F
+
+/*MAD channel change sel*/
+#define MAD_CH_COM_NUM_MASK		0xF
+#define MAD_CH_COM_NON			0x0
+#define MAD_CH_COM_2CH_TO_4CH		0x1
+#define MAD_CH_COM_2CH_TO_6CH		0x2
+#define MAD_CH_COM_2CH_TO_8CH		0x3
+#define MAD_CH_COM_4CH_TO_6CH		0x4
+#define MAD_CH_COM_4CH_TO_8CH		0x5
+
+/*SUNXI_MAD_LPSD_CH_MASK: 0x40*/
+#define MAD_LPSD_DCBLOCK_EN		20
+#define MAD_LPSD_CH_NUM			16
+#define MAD_LPSD_CH_MASK		0
+/*LPSD receive 0/1 audio channel mask*/
+#define MAD_LPSD_CH_NUM_MASK		0xF
+/*LPSD AUDIO channel num sel*/
+#define MAD_LPSD_CH_NUM_NON		0x0
+#define MAD_LPSD_CH_NUM_1CH		0x1
+
+/*SUNXI_MAD_SRAM_SEC_REGION: 0x44*/
+#define MAD_SRAM_SEC_REGION		0
+
+/*SUNXI_MAD_SRAM_PRE_DATA_SIZE(unit: half word): 0x48*/
+#define MAD_SRAM_PRE_DATA_SIZE		0
+
+/*SUNXI_MAD_DMA_TF_SIZE: 0x4C*/
+#define MAD_DMA_TF_SIZE			0
+
+/*SUNXI_MAD_DMA_TF_LAST_SIZE: 0x50*/
+#define MAD_DMA_TF_LAST_SIZE		0
+
+/*SUNXI_MAD_INT_ST_CLR: 0x60*/
+#define DATA_REQ_INT			1
+#define WAKE_INT			0
+
+/*SUNXI_MAD_INT_MASK: 0x64*/
+#define DATA_REQ_INT_MASK		1
+#define MAD_REQ_INT_MASK		0
+
+/*SUNXI_MAD_STATE_REG: 0x68*/
+#define MAD_LPSD_STAT			8
+#define MAD_STATE			4
+#define MAD_SRAM_FULL			2
+#define MAD_SRAM_EMPTY			1
+#define MAD_RUN				0
+/*MAD STATE(read only)*/
+#define MAD_STATE_IDLE			0x0
+#define MAD_STATE_WAIT			0x1
+#define MAD_STATE_RUN			0x2
+#define MAD_STATE_NORMAL		0x4
+
+/*SUNXI_MAD_DEBUG: 0x6C*/
+#define MAD_CFG_ERR			4
+#define MAD_SRAM_FULL_ERR		3
+#define MAD_SRAM_EMPTY_ERR		2
+#define DATA_SRAM_ADDR_ERR		1
+#define MAD_SRAM_SEC_ERR		0
+/*MAD_CFG_ERR mask*/
+#define MAD_CFG_ERR_MASK		0x3
+
+/* for mad clk*/
+#define MAD_SRAM_BMODE_CTRL 24
+#define SRAM_BMODE_CTRL_REG 0x3000004
+
+enum sunxi_mad_sram_reset_flag {
+	SUNXI_MAD_SRAM_RESET_IDLE = 0,
+	SUNXI_MAD_SRAM_RESET_START = 1,
+	SUNXI_MAD_SRAM_RESET_END = 2,
+};
+
+enum sunxi_mad_status {
+	SUNXI_MAD_OPEN = 0,
+	SUNXI_MAD_PARAMS = 1,
+	SUNXI_MAD_SUSPEND = 2,
+	SUNXI_MAD_RESUME = 3,
+	SUNXI_MAD_CLOSE = 4,
+};
+
+enum sunxi_mad_dma_type {
+	SUNXI_MAD_DMA_MEM = 0,
+	SUNXI_MAD_DMA_IO = 1,
+};
+
+enum sunxi_mad_standby_flag {
+	/* bit0 for sram IO type when standby */
+	SUNXI_MAD_STANDBY_SRAM_MEM = 0x1,
+};
+
+enum sunxi_mad_wakeup_flag {
+	/* bit0 for wakeup source */
+	SUNXI_MAD_WAKEUP_OFF = 0x0,
+	SUNXI_MAD_WAKEUP_ON = 0x1,
+	/* bit1 for wakeup use or no */
+	SUNXI_MAD_WAKEUP_USE = 0x2,
+
+	/* bit2 for lpsd wakeup */
+	SUNXI_MAD_WAKEUP_LPSD_IRQ = 0x4,
+	/* bit3 for mad irq wakeup */
+	SUNXI_MAD_WAKEUP_MAD_IRQ = 0x8,
+	/* bit4 for other irq wakeup */
+	SUNXI_MAD_WAKEUP_OTHER = 0x10,
+};
+
+struct sunxi_mad_info {
+	struct device *dev;
+	struct clk *mad_clk;
+	struct clk *mad_cfg_clk;
+	struct clk *mad_ad_clk;
+	struct clk *lpsd_clk;
+	struct clk *pll_clk;
+	struct clk *hosc_clk;
+
+	unsigned int pll_audio_src_used;
+	unsigned int hosc_src_used;
+
+	void __iomem *membase;
+	struct regmap *regmap;
+
+	unsigned int mad_irq;
+	unsigned int lpsd_irq;
+
+	unsigned int sram_rd_point;
+
+	unsigned int mad_bind;
+	unsigned int audio_src_path;
+	unsigned int audio_src_chan_num;
+	unsigned int standby_chan_sel;
+	unsigned int lpsd_chan_sel;
+
+	int status;
+	struct timeval suspend_tv;
+	unsigned int wakeup_flag;
+	unsigned int suspend_flag;
+	unsigned int sram_reset_flag;
+	int standby_sram_type;
+	int wakeup_irq_en;
+
+	spinlock_t resume_spin;
+
+	struct work_struct ws_resume;
+	struct work_struct ws_suspend;
+};
+
+extern int sunxi_mad_sram_set_reset_flag(enum sunxi_mad_sram_reset_flag reset_flag);
+extern enum sunxi_mad_sram_reset_flag sunxi_mad_sram_get_reset_flag(void);
+extern int sunxi_mad_sram_wait_reset_flag(enum sunxi_mad_sram_reset_flag reset_flag,
+			unsigned int time_out_msecond);
+
+extern void sunxi_mad_sram_chan_params(unsigned int mad_channels);
+extern struct sunxi_mad_info *sunxi_mad_get_mad_info(void);
+
+extern void sunxi_mad_clk_enable(bool val);
+extern void sunxi_mad_ad_clk_enable(bool val);
+extern void sunxi_mad_cfg_clk_enable(bool val);
+extern void sunxi_mad_module_clk_enable(bool val);
+extern void sunxi_lpsd_clk_enable(bool val);
+
+/* for mad interrupt */
+extern void sunxi_lpsd_int_stat_clr(void);
+extern void sunxi_mad_set_lpsdreq(bool enable);
+extern void sunxi_mad_set_datareq(bool enable);
+
+/* for mad init */
+extern int sunxi_mad_open(void);
+extern int sunxi_mad_close(void);
+extern void sunxi_mad_sram_init(void);
+extern void sunxi_mad_lpsd_init(void);
+extern void sunxi_sram_ahb1_threshole_init(void);
+extern void sunxi_mad_standby_chan_sel(unsigned int num);
+extern void sunxi_lpsd_chan_sel(unsigned int num);
+extern void sunxi_mad_audio_src_chan_num(unsigned int num);
+extern void sunxi_sram_dma_config(struct sunxi_dma_params *capture_dma_param);
+extern int sunxi_mad_hw_params(unsigned int mad_channels, unsigned int sample_rate);
+extern int sunxi_mad_audio_source_sel(unsigned int path_sel, unsigned int enable);
+extern int sunxi_mad_suspend_external(void);
+extern int sunxi_mad_resume_external(void);
+extern void sunxi_mad_dma_enable(bool enable);
+extern void sunxi_mad_dma_type(enum sunxi_mad_dma_type dma_type);
+extern int sunxi_mad_enable(bool enable);
+extern void sunxi_mad_set_go_on_sleep(bool enable);
+extern void sunxi_mad_sram_set_reset_bit(void);
+#endif /* SUNXI_MAD_H */