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firmware/br-ext-chip-allwinner/board/v83x/kernel/patches/00000-drivers_pinctrl_sunxi...

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diff -drupN a/drivers/pinctrl/sunxi/pinctrl-sun50iw1p1-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50iw1p1-r.c
--- a/drivers/pinctrl/sunxi/pinctrl-sun50iw1p1-r.c 1970-01-01 03:00:00.000000000 +0300
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50iw1p1-r.c 2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,159 @@
+/*
+ * Allwinner sun50iw1p1 SoCs R_PIO pinctrl driver.
+ *
+ * Copyright (C) 2014 Jackie Hwang
+ *
+ * Jackie Hwang <huangshr@allwinnertech.com>
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+static const struct sunxi_desc_pin sun50iw1p1_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb0"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_twi0"), /* SCK */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb0"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_twi0"), /* SDA */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* MS */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* CK */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* DO */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* DI */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi0"), /* SCK */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_twi0"), /* SDA */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_pwm0"),
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_cir0"), /* RX */
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x7, "io_disabled"),
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
+};
+
+#define IRQ_BANK_NUM 1
+static const unsigned sun50iw1p1_r_irq_bank_base[IRQ_BANK_NUM] = {0};
+
+static const struct sunxi_pinctrl_desc sun50iw1p1_r_pinctrl_data = {
+ .pins = sun50iw1p1_r_pins,
+ .npins = ARRAY_SIZE(sun50iw1p1_r_pins),
+ .pin_base = PL_BASE,
+ .irq_banks = IRQ_BANK_NUM,
+ .irq_bank_base = sun50iw1p1_r_irq_bank_base,
+};
+
+static int sun50iw1p1_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun50iw1p1_r_pinctrl_data);
+}
+
+static struct of_device_id sun50iw1p1_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-r-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun50iw1p1_r_pinctrl_match);
+
+static struct platform_driver sun50iw1p1_r_pinctrl_driver = {
+ .probe = sun50iw1p1_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-r-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = sun50iw1p1_r_pinctrl_match,
+ },
+};
+static int __init sun50iw1p1_r_pio_init(void)
+{
+ int ret;
+ ret = platform_driver_register(&sun50iw1p1_r_pinctrl_driver);
+ if (ret) {
+ pr_debug("register sun50iw1p1 r-pio controller failed\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+postcore_initcall(sun50iw1p1_r_pio_init);
+
+
+MODULE_AUTHOR("Jackie Hwang <huangshr@allwinnertech.com>");
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
+MODULE_DESCRIPTION("Allwinner sun50iw1p1 R_PIO pinctrl driver");
+MODULE_LICENSE("GPL");
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