mirror of https://github.com/OpenIPC/firmware.git
128 lines
4.6 KiB
Diff
128 lines
4.6 KiB
Diff
diff -drupN a/drivers/clk/sunxi/clk-sun8iw6.h b/drivers/clk/sunxi/clk-sun8iw6.h
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--- a/drivers/clk/sunxi/clk-sun8iw6.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/clk/sunxi/clk-sun8iw6.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,123 @@
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+/*
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+ * Copyright (C) 2013 Allwinnertech, kevin.z.m <kevin@allwinnertech.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * Adjustable factor-based clock implementation
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+ */
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+#ifndef __MACH_SUNXI_CLK_SUN8IW6_H
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+#define __MACH_SUNXI_CLK_SUN8IW6_H
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clkdev.h>
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+#include <linux/io.h>
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+#include "clk-factors.h"
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+
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+#define IO_ADDRESS(x) (void __iomem *)(((x) & 0x0fffffff) + \
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+ (((x) >> 4) & 0x0f000000) + \
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+ 0xf0000000)
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+
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+/* CCMU Register List */
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+#define PLL_CPU0 0x0000
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+#define PLL_CPU1 0x0004
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+#define PLL_AUDIO 0x0008
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+#define PLL_VIDEO0 0x0010
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+#define PLL_VE 0x0018
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+#define PLL_DDR 0x0020
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+#define PLL_PERIPH 0x0028
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+#define PLL_GPU 0x0038
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+#define PLL_HSIC 0x0044
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+#define PLL_DE 0x0048
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+#define PLL_VIDEO1 0x004c
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+
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+#define CPU_CFG 0x0050
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+#define AHB1_CFG 0x0054
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+#define APB2_CFG 0x0058
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+#define AHB2_CFG 0x005c
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+#define AHB1_GATE0 0x0060
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+#define AHB1_GATE1 0x0064
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+#define APB1_GATE 0x0068
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+#define APB2_GATE 0x006c
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+#define CCI400_CFG 0x0078
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+#define NAND_CFG 0x0080
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+#define SD0_CFG 0x0088
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+#define SD1_CFG 0x008c
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+#define SD2_CFG 0x0090
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+#define SS_CFG 0x009c
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+#define SPI0_CFG 0x00A0
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+#define SPI1_CFG 0x00A4
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+#define I2S0_CFG 0x00B0
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+#define I2S1_CFG 0x00B4
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+#define I2S2_CFG 0x00B8
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+#define TDM_CFG 0x00BC
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+#define SPDIF_CFG 0x00C0
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+#define USB_CFG 0x00CC
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+#define DRAM_CFG 0x00F4
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+#define DDR_CFG 0x00F8
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+#define MBUS_RST 0x00FC
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+
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+#define DRAM_GATE 0x0100
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+#define LCD0_CFG 0x0118
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+#define LCD1_CFG 0x011C
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+#define MIPICSI_CFG 0x0130
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+#define CSI_CFG 0x0134
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+#define VE_CFG 0x013C
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+#define AVS_CFG 0x0144
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+#define HDMI_CFG 0x0150
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+#define HDMI_SLOW 0x0154
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+#define MBUS_CFG 0x015C
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+#define MIPI_DSI0 0x0168
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+#define MIPI_DSI1 0x016c
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+#define GPU_CORE 0x01A0
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+#define GPU_MEM 0x01A4
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+#define GPU_HYD 0x01A8
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+
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+#define PLL_LOCK 0x0200
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+#define CPU_LOCK 0x0204
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+#define LOCK_STAT 0x020c
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+#define PLL_AUDIOPAT 0x0284
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+#define PLL_VIDEO0PAT 0x0288
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+#define AHB1_RST0 0x02C0
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+#define AHB1_RST1 0x02C4
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+#define AHB1_RST2 0x02C8
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+#define APB1_RST 0x02D0
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+#define APB2_RST 0x02D8
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+#define SUNXI_CLK_MAX_REG 0x02D8
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+
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+/* PRCM Register List */
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+#define CPUS_CFG 0x0000
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+#define CPUS_APB0 0x000C
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+#define CPUS_APB0_GATE 0x0028
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+#define CPUS_CIR 0x0054
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+#define CPUS_APB0_RST 0x00B0
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+#define CPUS_CLK_MAX_REG 0x00B0
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+
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+/* RTC Register List */
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+#define LOSC_OUT_GATE 0x0060
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+
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+/* AC100 Register List */
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+#define CK32K_OUT_CTRL1 0xC1
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+#define CK32K_OUT_CTRL2 0xC2
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+#define CK32K_OUT_CTRL3 0xC3
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+
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+#define F_N8X8_P16x1(nv, pv) \
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+ FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 1, 0, 0, 0, 0, 0, 0)
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+#define F_N8X8_P0x2_D1S16X1(nv, pv, d1v) \
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+ FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 0, 2, d1v, 16, 1, 0, 0, 0)
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+#define F_N8X6_D1S16X1_D2S18X1(nv, d1v, d2v) \
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+ FACTOR_ALL(nv, 8, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 16, 1, d2v, 18, 1)
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+#define F_N8X8_D1S16X1_D2S18X1(nv, d1v, d2v) \
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+ FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 16, 1, d2v, 18, 1)
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+
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+#define PLLCPU(n, p, freq) {F_N8X8_P16x1(n, p), freq}
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+#define PLLVIDEO(n, p, d1, freq) {F_N8X8_P0x2_D1S16X1(n, p, d1), freq}
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+#define PLLVE(n, d1, d2, freq) {F_N8X8_D1S16X1_D2S18X1(n, d1, d2), freq}
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+#define PLLDDR(n, d1, d2, freq) {F_N8X6_D1S16X1_D2S18X1(n, d1, d2), freq}
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+#define PLLPERIPH(n, d1, d2, freq) {F_N8X8_D1S16X1_D2S18X1(n, d1, d2), freq}
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+#define PLLGPU(n, d1, d2, freq) {F_N8X8_D1S16X1_D2S18X1(n, d1, d2), freq}
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+#define PLLHSIC(n, d1, d2, freq) {F_N8X8_D1S16X1_D2S18X1(n, d1, d2), freq}
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+#define PLLDE(n, d1, d2, freq) {F_N8X8_D1S16X1_D2S18X1(n, d1, d2), freq}
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+
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+#endif
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