mirror of https://github.com/OpenIPC/firmware.git
364 lines
8.3 KiB
C
364 lines
8.3 KiB
C
/******************************************************************************
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Copyright (C), 2015-2020, XM. Co., Ltd.
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******************************************************************************
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File Name : xm_defines.h
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Version : Initial Draft
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Author : XM Isp software group
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Created : 2015/6/27
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Description : The common data type defination
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Function List :
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History :
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1.Date : 2015/6/27
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Author : Lycai
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Modification : creat
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******************************************************************************/
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#ifndef __XM_DEFINES_H__
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#define __XM_DEFINES_H__
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#include "xm_type.h"
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#define LINE_LEN_BIT 5
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#define LINE_LEN (1<<LINE_LEN_BIT)
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#define LINE_BASE_MASK (~(LINE_LEN-1))
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typedef enum {
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DSP_XM510 = 0x100,
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DSP_XM530,
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DSP_XM580,
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DSP_XM320,
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DSP_XM322,
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DSP_XM350,
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DSP_XM380,
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DSP_XM310 = 0x110, // Ìṩ¸øPQ_Tool
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DSP_XM310V300 = 0x113, // Ìṩ¸øPQ_Tool
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DSP_XM330V200 = 0x122, // Ìṩ¸øPQ_Tool
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DSP_XM550 = 0x155,
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NR_DSPCHIP
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}XM_DSP_CHIP;
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typedef enum {
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SENSORCLK_18M = 0,
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SENSORCLK_24M = 1,
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SENSORCLK_27M = 2,
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SENSORCLK_37x125M = 3,
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SENSORCLK_24M_42M = 4,
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SENSORCLK_18x5625M = 5,
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}XM_SENSOR_CLK;
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typedef enum {
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SNSIO_12V = 0,
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SNSIO_15V,
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SNSIO_18V,
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SNSIO_28V,
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SNSIO_33V,
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}XM_SENSOR_IO;
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typedef enum {
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MIPI_8BIT = 0,
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MIPI_10BIT,
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MIPI_12BIT,
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}XM_MIPI_DEPTH;
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typedef enum {
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MIPI_1LANE = 0,
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MIPI_2LANE,
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MIPI_4LANE,
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}XM_MIPI_LANE;
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typedef enum xm_XM_SENSOR_BWIDE
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{
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SENSBWIDE_8BIT = 0,
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SENSBWIDE_10BIT ,
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SENSBWIDE_12BIT ,
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}XM_SENSOR_BWIDE;
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typedef enum xm_XM_SENSOR_CONT
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{
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SENSCONT_DVP = 0,
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SENSCONT_MIPI = 1,
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SENSCONT_BUTT = 0xFF,
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}XM_SENSOR_CONT;
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typedef enum xm_XM_FUNEXT
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{
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FUNBIT_XVI_MASK = 0,
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FUNBIT_AF_MASK = 1,
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FUNBIT_BUTT
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}XM_FUNEXT;
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typedef enum xm_PROFILE
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{
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P720_ = 0,
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P1080_ ,
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P960_ ,
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P1536_ ,
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P4M_ ,
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P5M_ ,
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P4K_ ,
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PCVBS_=100,
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P1080_S1 = 101, // 1080*1080
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P1080_S2 = 102, // 1280*1080
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PNULL ,
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}PROFILE ;
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typedef enum xm_VSTD
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{
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VSTDNULL = 0,
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PALS ,
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NTSCS ,
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NRT15 ,
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NRT12p5 ,
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}VSTD;
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typedef enum xm_txvenc_type
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{
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TXVENC_AHD = 0,
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TXVENC_CVI = 1,
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TXVENC_TVI = 2,
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TXVENC_CVBS = 3,
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TXVENC_AHD_15FPS = 4,
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//TXVENC_TVI_V1 = 7,
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TXVENC_BUTT
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}TXVENC_TYPE;
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typedef enum xm_ipcvenc_type
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{
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IPC_Hx264 = 0,
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IPC_Hx265 = 1,
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IPCVENC_BUTT
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}IPCVENC_TYPE;
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typedef struct xm_UPSCALER_CFG
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{
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PROFILE VPIXEL; // 0:720P 1:1080P 2:960P 3:NULL
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VSTD VSTDB; // 0:NULL 1:PAL 2:NTSC
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}UPSCALER_CFG;
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typedef struct xm_SENSOR_IO_V
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{
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XM_U8 SsDvdd;
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XM_U8 SsAvdd;
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XM_U8 SsDovdd;
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}XM_SENSOR_IO_V;
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typedef struct xm_SENSOR_MIPI
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{
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XM_U8 MpDepth;
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XM_U8 MpLane;
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}XM_SENSOR_MIPI;
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typedef struct xm_product_info
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{
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XM_U32 u32ProductType;
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XM_U32 u32DSPType;
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XM_U32 u32SensorType;
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XM_U8 u8SensorClk;
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XM_U8 u8SnsCommMode; // 0:I2C 1:SPI
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XM_SENSOR_IO_V stSnsIO; // 1.8v/3.3v
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XM_U8 u8StdType; //0: unknow 1:PAL 2:NTSC
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PROFILE u8RsltType; // 0: 720P 1:1080P 2:960P 3:1536P 101:P1080_S1 102:P1080_S2
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XM_BOOL bHsyncRecEn; // 0:Disable 1:Enable
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XM_SENSOR_BWIDE SnsBwide; //0:8bit 1:10bit 2:12bit
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XM_SENSOR_CONT SnsConnect; //0:DVP 1:MIPI
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XM_SENSOR_MIPI SnsMipi;
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XM_U8 u8FunExt; // XM_FUNEXT
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XM_U8 u8SnsHDRmark; //0:normal 1:build-in 2:wdr
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XM_U8 u8Encoder; //0:AHD 1:CVI 2:TVI 3;CVBS
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/****************************
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u8IRLed:
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bit0:
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0 ÆÕͨģʽ£¨ºìÍâͬ²½/×Ô¶¯Í¬²½... (Ó²¼þ¿ØÖƺìÍâµÆ)£©
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1 Èí¼þ¿ØÖƵÆ
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bit4:
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0 Èí¹âÃô
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1 Ó²¹âÃô
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****************************/
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XM_U8 u8IRLed;
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}XM_PRODUCT_INFO;
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typedef enum xm_oem
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{
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General = 0,
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JvFeng,
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XMJP,
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}OEM;
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#if 0
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inline void InvalidateDcache(unsigned long addr, unsigned long len)
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{
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unsigned long end;
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//TODO: cacheË¢ÐÂÐèÒªÖØд
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return ;
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addr &= LINE_BASE_MASK;
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len >>= LINE_LEN_BIT;
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end = addr + len*LINE_LEN;
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while(addr != end)
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{
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asm("mcr p15, 0, %0, c7, c6, 1"::"r"(addr));
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addr += LINE_LEN;
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}
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return;
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}
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inline void FlushDcache(unsigned long addr, unsigned long len)
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{
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unsigned long end;
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//TODO: cacheË¢ÐÂÐèÒªÖØд
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return ;
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addr &= LINE_BASE_MASK;
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len >>= LINE_LEN_BIT;
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end = addr + len*LINE_LEN;
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while(addr != end)
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{
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asm("mcr p15, 0, %0, c7, c10, 1"::"r"(addr));
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addr += LINE_LEN;
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}
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return;
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}
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#endif
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/* For Sys */
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#define DEFAULT_ALIGN 16
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#define MAX_MMZ_NAME_LEN 16
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#define MAX_NODE_NUM 16
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/* For VDA */
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#define VDA_MAX_NODE_NUM 32
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#define VDA_MAX_INTERNAL 256
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#define VDA_CHN_NUM_MAX 32
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#define VDA_MAX_WIDTH 960
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#define VDA_MAX_HEIGHT 576
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/* For VENC */
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#define VENC_MAX_NAME_LEN 16
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#define VENC_MAX_CHN_NUM 64
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#define VENC_MAX_GRP_NUM 64
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#define H264E_MAX_WIDTH 1920
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#define H264E_MAX_HEIGHT 2048
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#define H264E_MIN_WIDTH 160
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#define H264E_MIN_HEIGHT 64
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#define JPEGE_MAX_WIDTH 8192
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#define JPEGE_MAX_HEIGHT 8192
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#define JPEGE_MIN_WIDTH 64
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#define JPEGE_MIN_HEIGHT 64
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#define VENC_MAX_ROI_NUM 8 /* ×î´óÖ§³Ö8¸öROIÇøÓò */
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#define H264E_MIN_HW_INDEX 0
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#define H264E_MAX_HW_INDEX 5
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#define H264E_MIN_VW_INDEX 0
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#define H264E_MAX_VW_INDEX 2
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/* For VDEC, hi3518 not support */
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#define VDEC_MAX_CHN_NUM 0
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/* For Region */
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#define RGN_HANDLE_MAX 1024
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#define OVERLAY_MAX_NUM 8
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#define COVEREX_MAX_NUM 16
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#define COVER_MAX_NUM 4
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#define OVERLAYEX_MAX_NUM 0
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/* number of channle and device on video input unit of chip
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* Note! VIU_MAX_CHN_NUM is NOT equal to VIU_MAX_DEV_NUM
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* multiplied by VIU_MAX_CHN_NUM, because all VI devices
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* can't work at mode of 4 channles at the same time.
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*/
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#define VIU_MAX_DEV_NUM 1
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#define VIU_MAX_WAY_NUM_PER_DEV 1
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#define VIU_MAX_CHN_NUM_PER_DEV 1
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#define VIU_MAX_PHYCHN_NUM 1
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#define VIU_EXT_CHN_START VIU_MAX_PHYCHN_NUM
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#define VIU_MAX_EXT_CHN_NUM 16
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#define VIU_MAX_EXTCHN_BIND_PER_CHN 8
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#define VIU_MAX_CHN_NUM (VIU_MAX_PHYCHN_NUM + VIU_MAX_EXT_CHN_NUM)
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#define VIU_CHNID_DEV_FACTOR 2
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/* 3518±¾²»Ö§³Ö¼¶Áª£¬ÕâÀïºê¶¨ÒåÕâЩÐÅÏ¢£¬Ö»ÊÇΪÁ˱àÒëͨ¹ý */
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#define VIU_MAX_CAS_CHN_NUM 2
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#define VIU_SUB_CHN_START 16 /* ¶¨Òå´ÎͨµÀÆðʼºê*/
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#define VIU_CAS_CHN_START 32 /* ¶¨Ò弶ÁªÍ¨µÀÆðʼºê*/
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/* max number of VBI region*/
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#define VIU_MAX_VBI_NUM 2
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/* max length of one VBI region (by word)*/
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#define VIU_MAX_VBI_LEN 8
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#define VO_MIN_CHN_WIDTH 32 /* channel minimal width */
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#define VO_MIN_CHN_HEIGHT 32 /* channel minimal height */
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#define VO_MAX_ZOOM_RATIO 1000 /* max zoom ratio, 1000 means 100% scale */
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#define VO_MAX_DEV_NUM 1 /* max dev num */
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#define VO_MAX_LAYER_NUM 1 /* max layer num */
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#define VO_MAX_CHN_NUM 32 /* mac chn num */
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#define PIP_MAX_CHN_NUM 0
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#define VHD_MAX_CHN_NUM 0 /* max VHD chn num */
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#define VO_MAX_LAYER_IN_DEV 2 /* max layer num of each dev */
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#define VO_CAS_MAX_PAT 128 /* cascade pattern max number */
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#define VO_CAS_MAX_POS_32RGN 32 /* cascade position max number */
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#define VO_CAS_MAX_POS_64RGN 64 /* cascade position max number */
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#define VO_MAX_VIRT_DEV_NUM 4 /* max virtual dev num*/
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#define VO_VIRT_DEV_0 3 /* virtual display device 1 */
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#define VO_VIRT_DEV_1 4 /* virtual display device 2 */
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#define VO_VIRT_DEV_2 5 /* virtual display device 3 */
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#define VO_VIRT_DEV_3 6 /* virtual display device 4 */
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#define VO_MAX_GFX_LAYER_PER_DEV 1
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#define VOU_GRAPHICS_LAYER_NUM 1
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#define VO_MIN_TOLERATE 1 /* min play toleration 1ms */
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#define VO_MAX_TOLERATE 100000 /* max play toleration 100s */
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#define AIO_MAX_CHN_NUM 2
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#define AENC_MAX_CHN_NUM 32
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#define ADEC_MAX_CHN_NUM 32
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#define AI_DEV_MAX_NUM 1
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#define AO_DEV_MIN_NUM 0
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#define AO_DEV_MAX_NUM 1
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#define SIO_MAX_NUM 1
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#define VPSS_MAX_GRP_NUM 128
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#define VPSS_MAX_PHY_CHN_NUM 2
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#define VPSS_MAX_EXT_CHN_NUM 5
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#define VPSS_MAX_CHN_NUM (VPSS_MAX_PHY_CHN_NUM + VPSS_MAX_EXT_CHN_NUM + 1)
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#define VPSS_BSTR_CHN 0
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#define VPSS_LSTR_CHN 1
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#define VPSS_BYPASS_CHN 2
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#define PCIV_MAX_CHN_NUM 0 /* max pciv channel number in each pciv device */
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#define RC_MAD_HIST_SIZE 64
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#define RC_MSE_HIST_SIZE 128
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#define RC_MAX_BLINK_QP 35
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#ifdef CHIPID_XM580
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#define ISP_NUM_MAX (2) //(2)
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#else
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#define ISP_NUM_MAX (1) //(2)
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#endif
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#endif /* __XM_DEFINES_H__ */
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