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firmware/br-ext-chip-allwinner/board/v83x/kernel/patches/00000-sound_soc_sunxi_sunxi...

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diff -drupN a/sound/soc/sunxi/sunxi-daudio.h b/sound/soc/sunxi/sunxi-daudio.h
--- a/sound/soc/sunxi/sunxi-daudio.h 1970-01-01 03:00:00.000000000 +0300
+++ b/sound/soc/sunxi/sunxi-daudio.h 2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,480 @@
+/*
+ * sound\soc\sunxi\sunxi-daudio.h
+ * (C) Copyright 2014-2018
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * wolfgang huang <huangjinhui@allwinertech.com>
+ * yumingfeng <yumingfeng@allwinertech.com>
+ *
+ * some simple description for this code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+
+#ifndef __SUNXI_DAUDIO_H_
+#define __SUNXI_DAUDIO_H_
+/*
+ * Platform I2S_count HDMI_seq(index is 0 to i) MODE
+ * sun8iw7 3 2 A(TDM:8-channel)
+ * sun8iw8 1 NONE A(TDM:8-channel)
+ * sun8iw11 3 2 A(TDM:8-channel)
+ * sun50iw1 3 2 A(TDM:8-channel)
+ * sun50iw3 3 NONE B(TDM:16-channel)
+ * sun50iw8 3 NONE B(TDM:16-channels)
+ * sun50iw10 4 NONE B(TDM:16-channels)
+ * sun8iw16 3 1 B(TDM:16-channels)
+ * sun8iw18 3 NONE B(TDM:16-channels)
+ * sun8iw19 2 NONE B(TDM:16-channels)
+ */
+
+#if defined(CONFIG_ARCH_SUN8IW7) || defined(CONFG_ARCH_SUN8IW8) || \
+defined(CONFIG_ARCH_SUN8IW11) || defined(CONFIG_ARCH_SUN50IW1)
+/* 8-channel daudio mode */
+#define SUNXI_DAUDIO_MODE_A
+#else
+/* 16-channel daudio mode */
+#define SUNXI_DAUDIO_MODE_B
+#endif
+
+#if defined(CONFIG_ARCH_SUN8IW7) || defined(CONFIG_ARCH_SUN8IW11) || \
+defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN8IW16) || \
+defined(CONFIG_ARCH_SUN50IW1) || defined(CONFIG_ARCH_SUN50IW6)
+#define SUNXI_HDMI_AUDIO_ENABLE
+#else
+#undef SUNXI_HDMI_AUDIO_ENABLE
+#endif
+
+/* DAUDIO register definition */
+#define SUNXI_DAUDIO_CTL 0x00
+#define SUNXI_DAUDIO_FMT0 0x04
+#define SUNXI_DAUDIO_FMT1 0x08
+#define SUNXI_DAUDIO_INTSTA 0x0C
+#define SUNXI_DAUDIO_RXFIFO 0x10
+#define SUNXI_DAUDIO_FIFOCTL 0x14
+#define SUNXI_DAUDIO_FIFOSTA 0x18
+#define SUNXI_DAUDIO_INTCTL 0x1C
+#define SUNXI_DAUDIO_TXFIFO 0x20
+#define SUNXI_DAUDIO_CLKDIV 0x24
+#define SUNXI_DAUDIO_TXCNT 0x28
+#define SUNXI_DAUDIO_RXCNT 0x2C
+#define SUNXI_DAUDIO_CHCFG 0x30
+#define SUNXI_DAUDIO_TX0CHSEL 0x34
+#ifndef CONFIG_ARCH_SUN8IW18
+#define SUNXI_DAUDIO_TX1CHSEL 0x38
+#define SUNXI_DAUDIO_TX2CHSEL 0x3C
+#define SUNXI_DAUDIO_TX3CHSEL 0x40
+#endif
+
+#if defined(SUNXI_DAUDIO_MODE_B)
+#define SUNXI_DAUDIO_TX0CHMAP0 0x44
+#define SUNXI_DAUDIO_TX0CHMAP1 0x48
+#define SUNXI_DAUDIO_TX1CHMAP0 0x4C
+#define SUNXI_DAUDIO_TX1CHMAP1 0x50
+#define SUNXI_DAUDIO_TX2CHMAP0 0x54
+#define SUNXI_DAUDIO_TX2CHMAP1 0x58
+#define SUNXI_DAUDIO_TX3CHMAP0 0x5C
+#define SUNXI_DAUDIO_TX3CHMAP1 0x60
+#define SUNXI_DAUDIO_RXCHSEL 0x64
+#define SUNXI_DAUDIO_RXCHMAP0 0x68
+#define SUNXI_DAUDIO_RXCHMAP1 0x6C
+
+#if defined(CONFIG_ARCH_SUN8IW18) || defined(CONFIG_ARCH_SUN8IW19) || \
+ defined(CONFIG_ARCH_SUN50IW10)
+#define SUNXI_DAUDIO_RXCHMAP2 0x70
+#define SUNXI_DAUDIO_RXCHMAP3 0x74
+#define SUNXI_DAUDIO_DEBUG 0x78
+#define SUNXI_DAUDIO_REV 0x7C
+#else
+#define SUNXI_DAUDIO_DEBUG 0x70
+#endif
+
+#else
+#define SUNXI_DAUDIO_TX0CHMAP0 0x44
+#define SUNXI_DAUDIO_TX1CHMAP0 0x48
+#define SUNXI_DAUDIO_TX2CHMAP0 0x4C
+#define SUNXI_DAUDIO_TX3CHMAP0 0x50
+#define SUNXI_DAUDIO_RXCHSEL 0x54
+#define SUNXI_DAUDIO_RXCHMAP 0x58
+#define SUNXI_DAUDIO_DEBUG 0x5C
+#endif
+
+#define SUNXI_DAUDIO_REG_NUM_MAX (SUNXI_DAUDIO_DEBUG >> 2)
+
+/* SUNXI_DAUDIO_CTL:0x00 */
+#define RX_SYNC_EN 21
+#define RX_EN_MUX 20
+#define BCLK_OUT 18
+#define LRCK_OUT 17
+#define LRCKR_CTL 16
+#define SDO3_EN 11
+#define SDO2_EN 10
+#define SDO1_EN 9
+#define SDO0_EN 8
+#ifdef CONFIG_SND_SUNXI_MAD
+#define DAUDIO_MAD_DATA_EN 7
+#endif
+#define MUTE_CTL 6
+#define MODE_SEL 4
+#define LOOP_EN 3
+#define CTL_TXEN 2
+#define CTL_RXEN 1
+#define GLOBAL_EN 0
+
+/* SUNXI_DAUDIO_FMT0:0x04 */
+#define SDI_SYNC_SEL 31
+#define LRCK_WIDTH 30
+#define LRCKR_PERIOD 20
+#define LRCK_POLARITY 19
+#define LRCK_PERIOD 8
+#define BRCK_POLARITY 7
+#define DAUDIO_SAMPLE_RESOLUTION 4
+#define EDGE_TRANSFER 3
+#define SLOT_WIDTH 0
+
+/* SUNXI_DAUDIO_FMT1:0x08 */
+#define RX_MLS 7
+#define TX_MLS 6
+#define SEXT 4
+#define RX_PDM 2
+#define TX_PDM 0
+
+/* SUNXI_DAUDIO_INTSTA:0x0C */
+#define TXU_INT 6
+#define TXO_INT 5
+#define TXE_INT 4
+#define RXU_INT 2
+#define RXO_INT 1
+#define RXA_INT 0
+
+/* SUNXI_DAUDIO_FIFOCTL:0x14 */
+#define HUB_EN 31
+#define FIFO_CTL_FTX 25
+#define FIFO_CTL_FRX 24
+#define TXTL 12
+#define RXTL 4
+#define TXIM 2
+#define RXOM 0
+
+/* SUNXI_DAUDIO_FIFOSTA:0x18 */
+#define FIFO_TXE 28
+#define FIFO_TX_CNT 16
+#define FIFO_RXA 8
+#ifdef CONFIG_SND_SUNXI_MAD
+#define DAUDIO_MAD_DATA_ALIGN 7
+#endif
+#define FIFO_RX_CNT 0
+
+/* SUNXI_DAUDIO_INTCTL:0x1C */
+#define TXDRQEN 7
+#define TXUI_EN 6
+#define TXOI_EN 5
+#define TXEI_EN 4
+#define RXDRQEN 3
+#define RXUIEN 2
+#define RXOIEN 1
+#define RXAIEN 0
+
+/* SUNXI_DAUDIO_CLKDIV:0x24 */
+#define MCLKOUT_EN 8
+#define BCLK_DIV 4
+#define MCLK_DIV 0
+
+/* SUNXI_DAUDIO_CHCFG:0x30 */
+#define TX_SLOT_HIZ 9
+#define TX_STATE 8
+#define RX_SLOT_NUM 4
+#define TX_SLOT_NUM 0
+
+/* SUNXI_DAUDIO_TXnCHSEL:0X34+n*0x04 */
+#if defined(SUNXI_DAUDIO_MODE_B)
+#define TX_OFFSET 20
+#define TX_CHSEL 16
+#define TX_CHEN 0
+#else
+#define TX_OFFSET 12
+#define TX_CHEN 4
+#define TX_CHSEL 0
+#endif
+
+/* SUNXI_DAUDIO_RXCHSEL */
+#if defined(SUNXI_DAUDIO_MODE_B)
+#define RX_OFFSET 20
+#define RX_CHSEL 16
+#else
+#define RX_OFFSET 12
+#define RX_CHSEL 0
+#endif
+
+/* sun8iw10 CHMAP default setting */
+#define SUNXI_DEFAULT_CHMAP0 0xFEDCBA98
+#define SUNXI_DEFAULT_CHMAP1 0x76543210
+
+/* RXCHMAP default setting */
+#define SUNXI_DEFAULT_CHMAP 0x76543210
+
+/* Shift & Mask define */
+
+/* SUNXI_DAUDIO_CTL:0x00 */
+#define SUNXI_DAUDIO_MODE_CTL_MASK 3
+#define SUNXI_DAUDIO_MODE_CTL_PCM 0
+#define SUNXI_DAUDIO_MODE_CTL_I2S 1
+#define SUNXI_DAUDIO_MODE_CTL_LEFT 1
+#define SUNXI_DAUDIO_MODE_CTL_RIGHT 2
+#define SUNXI_DAUDIO_MODE_CTL_REVD 3
+/* combine LRCK_CLK & BCLK setting */
+#define SUNXI_DAUDIO_LRCK_OUT_MASK 3
+#define SUNXI_DAUDIO_LRCK_OUT_DISABLE 0
+#define SUNXI_DAUDIO_LRCK_OUT_ENABLE 3
+
+/* SUNXI_DAUDIO_FMT0 */
+#define SUNXI_DAUDIO_LRCK_PERIOD_MASK 0x3FF
+#define SUNXI_DAUDIO_SLOT_WIDTH_MASK 7
+/* Left Blank */
+#define SUNXI_DAUDIO_SR_MASK 7
+#define SUNXI_DAUDIO_SR_16BIT 3
+#define SUNXI_DAUDIO_SR_24BIT 5
+#define SUNXI_DAUDIO_SR_32BIT 7
+
+#define SUNXI_DAUDIO_LRCK_POLARITY_NOR 0
+#define SUNXI_DAUDIO_LRCK_POLARITY_INV 1
+#define SUNXI_DAUDIO_BCLK_POLARITY_NOR 0
+#define SUNXI_DAUDIO_BCLK_POLARITY_INV 1
+
+/* SUNXI_DAUDIO_FMT1 */
+#define SUNXI_DAUDIO_FMT1_DEF 0x30
+
+/* SUNXI_DAUDIO_FIFOCTL */
+#define SUNXI_DAUDIO_TXIM_MASK 1
+#define SUNXI_DAUDIO_TXIM_VALID_MSB 0
+#define SUNXI_DAUDIO_TXIM_VALID_LSB 1
+/* Left Blank */
+#define SUNXI_DAUDIO_RXOM_MASK 3
+/* Expanding 0 at LSB of RX_FIFO */
+#define SUNXI_DAUDIO_RXOM_EXP0 0
+/* Expanding sample bit at MSB of RX_FIFO */
+#define SUNXI_DAUDIO_RXOM_EXPH 1
+/* Fill RX_FIFO low word be 0 */
+#define SUNXI_DAUDIO_RXOM_TUNL 2
+/* Fill RX_FIFO high word be higher sample bit */
+#define SUNXI_DAUDIO_RXOM_TUNH 3
+
+/* SUNXI_DAUDIO_CLKDIV */
+#define SUNXI_DAUDIO_BCLK_DIV_MASK 0xF
+#define SUNXI_DAUDIO_BCLK_DIV_1 1
+#define SUNXI_DAUDIO_BCLK_DIV_2 2
+#define SUNXI_DAUDIO_BCLK_DIV_3 3
+#define SUNXI_DAUDIO_BCLK_DIV_4 4
+#define SUNXI_DAUDIO_BCLK_DIV_5 5
+#define SUNXI_DAUDIO_BCLK_DIV_6 6
+#define SUNXI_DAUDIO_BCLK_DIV_7 7
+#define SUNXI_DAUDIO_BCLK_DIV_8 8
+#define SUNXI_DAUDIO_BCLK_DIV_9 9
+#define SUNXI_DAUDIO_BCLK_DIV_10 10
+#define SUNXI_DAUDIO_BCLK_DIV_11 11
+#define SUNXI_DAUDIO_BCLK_DIV_12 12
+#define SUNXI_DAUDIO_BCLK_DIV_13 13
+#define SUNXI_DAUDIO_BCLK_DIV_14 14
+#define SUNXI_DAUDIO_BCLK_DIV_15 15
+/* Left Blank */
+#define SUNXI_DAUDIO_MCLK_DIV_MASK 0xF
+#define SUNXI_DAUDIO_MCLK_DIV_1 1
+#define SUNXI_DAUDIO_MCLK_DIV_2 2
+#define SUNXI_DAUDIO_MCLK_DIV_3 3
+#define SUNXI_DAUDIO_MCLK_DIV_4 4
+#define SUNXI_DAUDIO_MCLK_DIV_5 5
+#define SUNXI_DAUDIO_MCLK_DIV_6 6
+#define SUNXI_DAUDIO_MCLK_DIV_7 7
+#define SUNXI_DAUDIO_MCLK_DIV_8 8
+#define SUNXI_DAUDIO_MCLK_DIV_9 9
+#define SUNXI_DAUDIO_MCLK_DIV_10 10
+#define SUNXI_DAUDIO_MCLK_DIV_11 11
+#define SUNXI_DAUDIO_MCLK_DIV_12 12
+#define SUNXI_DAUDIO_MCLK_DIV_13 13
+#define SUNXI_DAUDIO_MCLK_DIV_14 14
+#define SUNXI_DAUDIO_MCLK_DIV_15 15
+
+/* SUNXI_DAUDIO_CHCFG */
+#ifdef SUNXI_DAUDIO_MODE_B
+#define SUNXI_DAUDIO_TX_SLOT_MASK 0XF
+#define SUNXI_DAUDIO_RX_SLOT_MASK 0XF
+#else
+#define SUNXI_DAUDIO_TX_SLOT_MASK 7
+#define SUNXI_DAUDIO_RX_SLOT_MASK 7
+#endif
+/* SUNXI_DAUDIO_TX0CHSEL: */
+#define SUNXI_DAUDIO_TX_OFFSET_MASK 3
+#define SUNXI_DAUDIO_TX_OFFSET_0 0
+#define SUNXI_DAUDIO_TX_OFFSET_1 1
+/* Left Blank */
+#ifdef SUNXI_DAUDIO_MODE_B
+#define SUNXI_DAUDIO_TX_CHEN_MASK 0xFFFF
+#define SUNXI_DAUDIO_TX_CHSEL_MASK 0xF
+#else
+#define SUNXI_DAUDIO_TX_CHEN_MASK 0xFF
+#define SUNXI_DAUDIO_TX_CHSEL_MASK 7
+#endif
+
+/* SUNXI_DAUDIO_RXCHSEL */
+#define SUNXI_DAUDIO_RX_OFFSET_MASK 3
+#ifdef SUNXI_DAUDIO_MODE_B
+#define SUNXI_DAUDIO_RX_CHSEL_MASK 0XF
+#else
+#define SUNXI_DAUDIO_RX_CHSEL_MASK 7
+#endif
+
+#if defined(CONFIG_ARCH_SUN8IW18) || defined(CONFIG_ARCH_SUN8IW19) || \
+ defined(CONFIG_ARCH_SUN50IW10)
+#define DAUDIO_RXCH_DEF_MAP(x) (x << ((x%4)<<3))
+#define DAUDIO_RXCHMAP(x) (0x1f << ((x%4)<<3))
+#endif
+
+/*
+ * For other define.
+ */
+
+#define SND_SOC_DAIFMT_SIG_SHIFT 8
+#define SND_SOC_DAIFMT_MASTER_SHIFT 12
+
+#if defined(CONFIG_ARCH_SUN8IW18)
+#define DAUDIO_PLL_AUDIO_X4
+#define USE_ASOC_FMT_SETTING
+#else
+#undef DAUDIO_PLL_AUDIO_X4
+#undef USE_ASOC_FMT_SETTING
+#endif
+
+#if defined(CONFIG_ARCH_SUN8IW19) || defined(CONFIG_ARCH_SUN50IW10)
+#define USE_ASOC_FMT_SETTING
+#endif
+
+#undef DAUDIO_PINCTRL_STATE_DEFAULT_B
+
+/* define for HDMI audio drq type number */
+#if defined(CONFIG_ARCH_SUN8IW11) || defined(CONFIG_ARCH_SUN8IW7) || \
+defined(CONFIG_ARCH_SUN50IW1)
+#define DRQDST_HDMI_TX DRQDST_DAUDIO_2_TX
+#define DRQDST_HDMI_RX DRQSRC_DAUDIO_2_RX
+#elif defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN8IW16) || \
+defined(CONFIG_ARCH_SUN50IW6)
+#define DRQDST_HDMI_TX DRQDST_DAUDIO_1_TX
+#define DRQDST_HDMI_RX DRQSRC_DAUDIO_1_RX
+#endif
+
+/* Debug */
+#if defined(CONFIG_ARCH_SUN8IW16)
+#undef DAUDIO_CLASS_DEBUG
+#endif
+
+#undef DAUDIO_STANDBY_DEBUG
+
+/*
+ * some platform just not support four channel daudio,
+ * so make the 3rd channel define as NULL for codec compile
+ */
+#if defined(CONFIG_ARCH_SUN8IW8)
+#define DRQSRC_DAUDIO_1_RX 0
+#define DRQDST_DAUDIO_1_TX 0
+#define DRQSRC_DAUDIO_2_RX 0
+#define DRQDST_DAUDIO_2_TX 0
+#define DRQSRC_DAUDIO_3_RX 0
+#define DRQDST_DAUDIO_3_TX 0
+#define DAUDIO_NUM_MAX 1
+#endif
+
+#if defined(CONFIG_ARCH_SUN8IW11) || defined(CONFIG_ARCH_SUN8IW12) || \
+defined(CONFIG_ARCH_SUN8IW16) || defined(CONFIG_ARCH_SUN8IW17) || \
+defined(CONFIG_ARCH_SUN8IW18) || defined(CONFIG_ARCH_SUN50IW8)
+#define DRQDST_DAUDIO_3_TX 0
+#define DRQSRC_DAUDIO_3_RX 0
+#define DAUDIO_NUM_MAX 3
+#endif
+
+#if defined(CONFIG_ARCH_SUN50IW1)
+#define DRQSRC_DAUDIO_2_RX 0
+#define DRQSRC_DAUDIO_3_RX 0
+#define DRQDST_DAUDIO_3_TX 0
+#define DAUDIO_NUM_MAX 3
+#endif
+
+#if defined(CONFIG_ARCH_SUN50IW3)
+#define DRQSRC_DAUDIO_3_RX 0
+#define DRQDST_DAUDIO_3_TX 0
+#define DAUDIO_NUM_MAX 3
+#endif
+
+/* sun8iw19p1 and sun8iw15p1 just use i2s0/i2s1 */
+#if defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN8IW19)
+#define DRQDST_HDMI_TX 0
+#define DRQDST_DAUDIO_2_TX 0
+#define DRQSRC_DAUDIO_2_RX 0
+#define DRQSRC_DAUDIO_3_RX 0
+#define DRQDST_DAUDIO_3_TX 0
+#define DAUDIO_NUM_MAX 2
+#endif
+
+#if defined(CONFIG_ARCH_SUN50IW8)
+#define DRQSRC_DAUDIO_3_RX 0
+#define DRQDST_DAUDIO_3_TX 0
+#define DAUDIO_NUM_MAX 3
+#endif
+
+#ifndef DAUDIO_NUM_MAX
+#define DAUDIO_NUM_MAX 4
+#endif
+
+#define SUNXI_DAUDIO_BCLK 0
+#define SUNXI_DAUDIO_LRCK 1
+#define SUNXI_DAUDIO_MCLK 2
+#define SUNXI_DAUDIO_GEN 3
+
+/*to clear FIFO*/
+#ifdef CONFIG_ARCH_SUN8IW7
+#define SUNXI_DAUDIO_FTX_TIMES 3
+#else
+#define SUNXI_DAUDIO_FTX_TIMES 1
+#endif
+
+struct reg_label {
+ const char *name;
+ const unsigned long address;
+ int value;
+};
+
+#define REG_LABEL(constant) {#constant, constant, 0}
+#define REG_LABEL_END {NULL, -1, 0}
+
+extern int daudio_set_clk_onoff(struct snd_soc_dai *dai, u32 mask, bool enable);
+
+#ifndef CONFIG_SND_SUNXI_SOC_SUNXI_HDMIAUDIO
+static inline int sunxi_hdmi_codec_hw_params(
+ struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+ return 0;
+}
+
+static inline int sunxi_hdmi_codec_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ return 0;
+}
+
+static inline void sunxi_hdmi_codec_shutdown(
+ struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
+{
+}
+
+#else /* !CONFIG_SND_SUNXI_SOC_SUNXI_HDMIAUDIO */
+extern int sunxi_hdmi_codec_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai);
+extern void sunxi_hdmi_codec_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai);
+extern int sunxi_hdmi_codec_prepare(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai);
+#endif /* CONFIG_SND_SUNXI_SOC_SUNXI_HDMIAUDIO */
+
+
+#endif /* __SUNXI_DAUDIO_H_ */
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