firmware/general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/sc1035_960p.ini

126 lines
5.2 KiB
INI

# Untested sensor 2021.01.25
[sensor]
Sensor_type =sc1035 ;sensor name
Mode =0 ;WDR_MODE_NONE = 0
;WDR_MODE_BUILT_IN = 1
;WDR_MODE_2To1_LINE = 2
;WDR_MODE_2To1_FRAME = 3
;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
DllFile =/usr/lib/sensors/libsns_sc1035_960p.so ;sensor lib path
[mode]
input_mode =4 ;INPUT_MODE_MIPI = 0
;INPUT_MODE_SUBLVDS = 1
;INPUT_MODE_LVDS = 2 ...etc
dev_attr = 2 ;mipi_dev_attr_t = 0
;lvds_dev_attr_t = 1
;NULL =2
[isp_image]
Isp_x =0
Isp_y =0
Isp_W =1280
Isp_H =720
Isp_FrameRate=30
Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3
[vi_dev]
Input_mod =2 ;VI_INPUT_MODE_BT656 = 0
;VI_INPUT_MODE_BT601,
;VI_INPUT_MODE_DIGITAL_CAMERA
Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
;VI_WORK_MODE_2Multiplex,
;VI_WORK_MODE_4Multiplex
Combine_mode =0 ;Y/C composite or separation mode
;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
;VI_COMBINE_SEPARATE, /*Separate mode */
Comp_mode =0 ;Component mode (single-component or dual-component)
;VI_COMP_MODE_SINGLE = 0, /*single component mode */
;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
Mask_num =2 ;Component mask
Mask_0 =0xFFF00000 ; Please also probe mask 0xFFF0000
Mask_1 =0x0
Scan_mode =1 ;VI_SCAN_INTERLACED = 0
;VI_SCAN_PROGRESSIVE,
Data_seq =2 ;data sequence (ONLY for YUV format)
;----2th component U/V sequence in bt1120
; VI_INPUT_DATA_VUVU = 0,
; VI_INPUT_DATA_UVUV,
;----input sequence for yuv
; VI_INPUT_DATA_UYVY = 0,
; VI_INPUT_DATA_VYUY,
; VI_INPUT_DATA_YUYV,
; VI_INPUT_DATA_YVYU
Vsync =1 ; vertical synchronization signal
;VI_VSYNC_FIELD = 0,
;VI_VSYNC_PULSE,
VsyncNeg=0 ;Polarity of the vertical synchronization signal
;VI_VSYNC_NEG_HIGH = 0,
;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
Hsync =0 ;Attribute of the horizontal synchronization signal
;VI_HSYNC_VALID_SINGNAL = 0,
;VI_HSYNC_PULSE,
HsyncNeg =0 ;Polarity of the horizontal synchronization signal
;VI_HSYNC_NEG_HIGH = 0,
;VI_HSYNC_NEG_LOW
VsyncValid =0 ;Attribute of the valid vertical synchronization signal
;VI_VSYNC_NORM_PULSE = 0,
;VI_VSYNC_VALID_SINGAL,
VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
;VI_VSYNC_VALID_NEG_HIGH = 0,
;VI_VSYNC_VALID_NEG_LOW
Timingblank_HsyncHfb =0 ;Horizontal front blanking width
Timingblank_HsyncAct =1280 ;Horizontal effetive width
Timingblank_HsyncHbb =0 ;Horizontal back blanking width
Timingblank_VsyncVfb =0 ;Vertical front blanking height
Timingblank_VsyncVact =960 ;Vertical effetive width
Timingblank_VsyncVbb=0 ;Vertical back blanking height
Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
;----- only for bt656 ----------
FixCode =0 ;BT656_FIXCODE_1 = 0,
;BT656_FIXCODE_0
FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0
;BT656_FIELD_POLAR_NSTD
DataPath =1 ;ISP enable or bypass
;VI_PATH_BYPASS = 0,/* ISP bypass */
;VI_PATH_ISP = 1,/* ISP enable */
;VI_PATH_RAW = 2,/* Capture raw data, for debug */
InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
DevRect_x=0 ;
DevRect_y=0 ;
DevRect_w=1280 ;
DevRect_h=960 ;
[vi_chn]
CapRect_X =0
CapRect_Y =0
CapRect_Width=1280
CapRect_Height=960
DestSize_Width=1280
DestSize_Height=960
CapSel =2 ;Frame/field select. ONLY used in interlaced mode
;VI_CAPSEL_TOP = 0, /* top field */
;VI_CAPSEL_BOTTOM, /* bottom field */
;VI_CAPSEL_BOTH, /* top and bottom field */
PixFormat =19;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22
;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc
CompressMode =0 ;COMPRESS_MODE_NONE = 0
;COMPRESS_MODE_SEG =1 ...etc
SrcFrameRate=-1 ;Source frame rate. -1: not controll
FrameRate =-1 ;Target frame rate. -1: not controll