mirror of https://github.com/OpenIPC/firmware.git
327 lines
12 KiB
Diff
327 lines
12 KiB
Diff
diff -drupN a/include/linux/ingenic_adc.h b/include/linux/ingenic_adc.h
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--- a/include/linux/ingenic_adc.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/include/linux/ingenic_adc.h 2022-06-09 05:02:35.000000000 +0300
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@@ -0,0 +1,322 @@
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+#ifndef __LINUX_INGENIC_ADC_H__
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+#define __LINUX_INGENIC_ADC_H__
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+
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+#include <linux/device.h>
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+
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+/*
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+ * SAR A/D Controller(SADC) address definition
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+ */
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+#define SADC_BASE 0xb0070000
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+
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+/*************************************************************************
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+ * SADC (Smart A/D Controller)
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+ *************************************************************************/
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+#define BIT0 (1 << 0)
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+#define BIT1 (1 << 1)
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+#define BIT2 (1 << 2)
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+#define BIT3 (1 << 3)
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+#define BIT4 (1 << 4)
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+#define BIT5 (1 << 5)
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+#define BIT6 (1 << 6)
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+#define BIT7 (1 << 7)
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+#define BIT8 (1 << 8)
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+#define BIT9 (1 << 9)
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+#define BIT10 (1 << 10)
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+#define BIT11 (1 << 11)
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+#define BIT12 (1 << 12)
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+#define BIT13 (1 << 13)
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+#define BIT14 (1 << 14)
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+#define BIT15 (1 << 15)
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+#define BIT16 (1 << 16)
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+#define BIT17 (1 << 17)
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+#define BIT18 (1 << 18)
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+#define BIT19 (1 << 19)
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+#define BIT20 (1 << 20)
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+#define BIT21 (1 << 21)
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+#define BIT22 (1 << 22)
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+#define BIT23 (1 << 23)
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+#define BIT24 (1 << 24)
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+#define BIT25 (1 << 25)
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+#define BIT26 (1 << 26)
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+#define BIT27 (1 << 27)
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+#define BIT28 (1 << 28)
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+#define BIT29 (1 << 29)
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+#define BIT30 (1 << 30)
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+#define BIT31 (1 << 31)
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+
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+
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+
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+
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+
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+#define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
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+#define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
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+#define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
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+#define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
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+#define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
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+#define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
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+#define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
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+#define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC VBAT Data Register */
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+#define SADC_SADDAT (SADC_BASE + 0x20) /* ADC AUX Data Register */
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+#define SADC_FLT (SADC_BASE + 0x24) /* ADC Filter Register */
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+
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+#define REG_SADC_ENA REG8(SADC_ENA)
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+#define REG_SADC_CFG REG32(SADC_CFG)
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+#define REG_SADC_CTRL REG8(SADC_CTRL)
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+#define REG_SADC_STATE REG8(SADC_STATE)
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+#define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
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+#define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
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+#define REG_SADC_TSDAT REG32(SADC_TSDAT)
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+#define REG_SADC_BATDAT REG16(SADC_BATDAT)
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+#define REG_SADC_SADDAT REG16(SADC_SADDAT)
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+#define REG_SADC_ADCLK REG32(SADC_ADCLK)
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+#define REG_SADC_FLT REG16(SADC_FLT)
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+ #define SADC_FLT_ENA (1 << 15)
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+
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+/* ADENA: ADC Enable Register */
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+#define SADC_ENA_POWER (1 << 7) /* SADC Power control bit */
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+#define SADC_ENA_SLP_MD (1 << 6) /* SLEEP mode control */
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+#define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
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+#define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
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+#define SADC_ENA_SADCINEN (1 << 0) /* AUX n Enable */
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+
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+/* ADC Configure Register */
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+#define SADC_CFG_SPZZ (1 << 31)
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+#define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
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+#define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
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+#define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
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+ #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
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+ #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
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+ #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
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+#define SADC_CFG_SNUM_BIT 10 /* Sample Number */
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+#define SADC_CFG_SNUM(x) (((x) - 1) << SADC_CFG_SNUM_BIT)
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+#define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
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+ #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
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+#define SADC_CFG_CMD_BIT 0 /* ADC Command */
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+#define SADC_CFG_CMD_MASK (0x3 << SADC_CFG_CMD_BIT)
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+ #define SADC_CFG_CMD_AUX0 (0x0 << SADC_CFG_CMD_BIT) /* AUX voltage */
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+ #define SADC_CFG_CMD_AUX1 (0x1 << SADC_CFG_CMD_BIT) /* AUX1 voltage */
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+ #define SADC_CFG_CMD_AUX2 (0x2 << SADC_CFG_CMD_BIT) /* AUX2 voltage */
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+ #define SADC_CFG_CMD_RESERVED (0x3 << SADC_CFG_CMD_BIT) /* Reserved */
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+
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+/* ADCCTRL: ADC Control Register */
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+#define SADC_CTRL_SLPENDM (1 << 5) /* Sleep Interrupt Mask */
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+#define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
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+#define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
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+#define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
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+#define SADC_CTRL_PBATRDYM (1 << 1) /* VBAT Data Ready Interrupt Mask */
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+#define SADC_CTRL_SRDYM (1 << 0) /* AUX Data Ready Interrupt Mask */
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+
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+/* ADSTATE: ADC Status Register */
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+#define SADC_STATE_SLP_RDY (1 << 7) /* Sleep state bit */
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+#define SADC_STATE_SLEEPND (1 << 5) /* Pen Down Interrupt Flag */
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+#define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
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+#define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
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+#define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
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+#define SADC_STATE_PBATRDY (1 << 1) /* VBAT Data Ready Interrupt Flag */
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+#define SADC_STATE_SRDY (1 << 0) /* AUX Data Ready Interrupt Flag */
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+
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+/* ADTCH: ADC Touch Screen Data Register */
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+#define SADC_TSDAT_TYPE1 (1 << 31)
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+#define SADC_TSDAT_DATA1_BIT 16
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+#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
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+#define SADC_TSDAT_TYPE0 (1 << 15)
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+#define SADC_TSDAT_DATA0_BIT 0
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+#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
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+
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+/* ADCLK: ADC Clock Divide Register */
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+#define SADC_ADCLK_CLKDIV_MS 16
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+#define SADC_ADCLK_CLKDIV_MS_MASK (0xffff << SADC_ADCLK_CLKDIV_MS)
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+#define SADC_ADCLK_CLKDIV_US 8
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+#define SADC_ADCLK_CLKDIV_US_MASK (0xff << SADC_ADCLK_CLKDIV_US)
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+#define SADC_ADCLK_CLKDIV_BIT 0
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+#define SADC_ADCLK_CLKDIV_MASK (0xff << SADC_ADCLK_CLKDIV_BIT)
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+
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+/*
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+ * SADC registers offset definition
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+ */
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+#define SADC_ADENA_OFFSET (0x00) /* rw, 8, 0x00 */
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+#define SADC_ADCFG_OFFSET (0x04) /* rw, 32, 0x0002000c */
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+#define SADC_ADCTRL_OFFSET (0x08) /* rw, 8, 0x3f */
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+#define SADC_ADSTATE_OFFSET (0x0c) /* rw, 8, 0x00 */
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+#define SADC_ADSAME_OFFSET (0x10) /* rw, 16, 0x0000 */
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+#define SADC_ADWAIT_OFFSET (0x14) /* rw, 16, 0x0000 */
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+#define SADC_ADTCH_OFFSET (0x18) /* rw, 32, 0x00000000 */
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+#define SADC_ADVDAT_OFFSET (0x1c) /* rw, 16, 0x0000 */
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+#define SADC_ADADAT_OFFSET (0x20) /* rw, 16, 0x0000 */
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+#define SADC_ADCMD_OFFSET (0x24) /* rw, 32, 0x00000000 */
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+#define SADC_ADCLK_OFFSET (0x28) /* rw, 32, 0x00000000 */
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+
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+/*
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+ * SADC registers address definition
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+ */
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+#define SADC_ADENA (SADC_BASE + SADC_ADENA_OFFSET) /* ADC Enable Register */
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+#define SADC_ADCFG (SADC_BASE + SADC_ADCFG_OFFSET) /* ADC Configure Register */
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+#define SADC_ADCTRL (SADC_BASE + SADC_ADCTRL_OFFSET) /* ADC Control Register */
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+#define SADC_ADSTATE (SADC_BASE + SADC_ADSTATE_OFFSET)/* ADC Status Register*/
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+#define SADC_ADSAME (SADC_BASE + SADC_ADSAME_OFFSET) /* ADC Same Point Time Register */
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+#define SADC_ADWAIT (SADC_BASE + SADC_ADWAIT_OFFSET) /* ADC Wait Time Register */
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+#define SADC_ADTCH (SADC_BASE + SADC_ADTCH_OFFSET) /* ADC Touch Screen Data Register */
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+#define SADC_ADVDAT (SADC_BASE + SADC_ADVDAT_OFFSET) /* ADC VBAT Data Register */
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+#define SADC_ADADAT (SADC_BASE + SADC_ADADAT_OFFSET) /* ADC AUX Data Register */
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+#define SADC_ADCMD (SADC_BASE + SADC_ADCMD_OFFSET) /* ADC COMMAND Register */
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+#define SADC_ADCLK (SADC_BASE + SADC_ADCLK_OFFSET) /* ADC Clock Divide Register */
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+
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+
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+/*
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+ * SADC registers common define
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+ */
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+
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+/* ADC Enable Register (ADENA) */
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+#define ADENA_POWER BIT7
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+#define ADENA_SLP_MD BIT6
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+#define ADENA_TCHEN BIT2
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+#define ADENA_PENDEN BIT3
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+#define ADENA_VBATEN BIT1
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+#define ADENA_AUXEN BIT0
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+
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+/* ADC Configure Register (ADCFG) */
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+#define ADCFG_SPZZ BIT31
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+
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+#define ADCFG_CMD_SEL BIT22
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+
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+#define ADCFG_DMA_EN BIT15
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+
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+#define ADCFG_XYZ_LSB 13
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+#define ADCFG_XYZ_MASK BITS_H2L(14, ADCFG_XYZ_LSB)
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+#define ADCFG_XYZ_XYS (0x0 << ADCFG_XYZ_LSB)
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+#define ADCFG_XYZ_XYD (0x1 << ADCFG_XYZ_LSB)
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+#define ADCFG_XYZ_XYZ1Z2 (0x2 << ADCFG_XYZ_LSB)
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+#define ADCFG_XYZ_XYZ1Z2X2Y2 (0x3 << ADCFG_XYZ_LSB)
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+
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+#define ADCFG_SNUM_LSB 10
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+#define ADCFG_SNUM_MASK BITS_H2L(12, ADCFG_SNUM_LSB)
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+#define ADCFG_SNUM(n) (((n) <= 6 ? ((n)-1) : ((n)-2)) << ADCFG_SNUM_LSB)
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+
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+#define ADCFG_CMD_LSB 0
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+#define ADCFG_CMD_MASK BITS_H2L(1, ADCFG_CMD_LSB)
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+#define ADCFG_CMD_AUX(n) ((n) << ADCFG_CMD_LSB)
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+
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+/* ADC Control Register (ADCCTRL) */
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+#define ADCTRL_SLPENDM BIT5
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+#define ADCTRL_PENDM BIT4
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+#define ADCTRL_PENUM BIT3
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+#define ADCTRL_DTCHM BIT2
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+#define ADCTRL_VRDYM BIT1
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+#define ADCTRL_ARDYM BIT0
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+#define ADCTRL_MASK_ALL (ADCTRL_SLPENDM | ADCTRL_PENDM | ADCTRL_PENUM \
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+ | ADCTRL_DTCHM | ADCTRL_VRDYM | ADCTRL_ARDYM)
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+
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+/* ADC Status Register (ADSTATE) */
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+#define ADSTATE_SLP_RDY BIT7
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+#define ADSTATE_SLPEND BIT5
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+#define ADSTATE_PEND BIT4
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+#define ADSTATE_PENU BIT3
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+#define ADSTATE_DTCH BIT2
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+#define ADSTATE_VRDY BIT1
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+#define ADSTATE_ARDY BIT0
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+
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+/* ADC Same Point Time Register (ADSAME) */
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+#define ADSAME_SCNT_LSB 0
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+#define ADSAME_SCNT_MASK BITS_H2L(15, ADSAME_SCNT_LSB)
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+
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+/* ADC Wait Pen Down Time Register (ADWAIT) */
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+#define ADWAIT_WCNT_LSB 0
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+#define ADWAIT_WCNT_MASK BITS_H2L(15, ADWAIT_WCNT_LSB)
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+
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+/* ADC Touch Screen Data Register (ADTCH) */
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+#define ADTCH_TYPE1 BIT31
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+#define ADTCH_TYPE0 BIT15
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+
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+#define ADTCH_DATA1_LSB 16
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+#define ADTCH_DATA1_MASK BITS_H2L(27, ADTCH_DATA1_LSB)
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+
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+#define ADTCH_DATA0_LSB 0
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+#define ADTCH_DATA0_MASK BITS_H2L(11, ADTCH_DATA0_LSB)
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+
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+/* ADC VBAT Date Register (ADVDAT) */
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+#define ADVDAT_VDATA_LSB 0
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+#define ADVDAT_VDATA_MASK BITS_H2L(11, ADVDAT_VDATA_LSB)
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+
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+/* ADC AUX Data Register (ADADAT) */
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+#define ADADAT_ADATA_LSB 0
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+#define ADADAT_ADATA_MASK BITS_H2L(11, ADADAT_ADATA_LSB)
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+
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+/* ADC Clock Divide Register (ADCLK) */
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+#define ADCLK_CLKDIV_MS_LSB 16
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+#define ADCLK_CLKDIV_MS_MASK BITS_H2L(31, ADCLK_CLKDIV_MS_LSB)
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+
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+#define ADCLK_CLKDIV_US_LSB 8
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+#define ADCLK_CLKDIV_US_MASK BITS_H2L(15, ADCLK_CLKDIV_US_LSB)
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+
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+#define ADCLK_CLKDIV_LSB 0
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+#define ADCLK_CLKDIV_MASK BITS_H2L(7, ADCLK_CLKDIV_LSB)
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+
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+/* ADC Filter Register (ADFLT) */
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+#define ADFLT_FLT_EN BIT15
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+
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+#define ADFLT_FLT_D_LSB 0
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+#define ADFLT_FLT_D_MASK BITS_H2L(11, ADFLT_FLT_D_LSB)
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+
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+/* ADC Command Register (ADCMD) */
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+#define ADCMD_PIL BIT31
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+#define ADCMD_RPU(n) ((n) << 26)
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+#define ADCMD_XPSUP BIT25
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+#define ADCMD_YPSUP BIT23
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+#define ADCMD_XNGRU BIT21
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+#define ADCMD_YNGRU BIT20
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+#define ADCMD_VREFNXN BIT18
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+#define ADCMD_VREFNYN BIT16
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+#define ADCMD_VREFPXP BIT12
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+#define ADCMD_VREFPYP BIT11
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+#define ADCMD_XPADC BIT10
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+#define ADCMD_YPADC BIT8
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+struct ingenic_ts_info{
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+ unsigned int x_max;
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+ unsigned int x_min;
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+ unsigned int y_max;
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+ unsigned int y_min;
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+ unsigned int z_max;
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+ unsigned int z_min;
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+ unsigned short x_resolution;
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+ unsigned short y_resolution;
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+ unsigned short y_r_plate;
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+ unsigned short x_r_plate;
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+ unsigned short pressure_max;
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+ unsigned int use_5_wire;
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+ unsigned int support_keypad;
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+ unsigned int support_mt_touch;
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+ unsigned int support_sleepmode;
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+ void *private_data;
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+};
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+
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+
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+
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+/*
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+ * ingenic_adc_set_config - Configure a ingenic adc device
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+ * @dev: Pointer to a ingenic-adc device
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+ * @mask: Mask for the config value to be set
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+ * @val: Value to be set
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+ *
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+ * This function can be used by the ingenic
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+ * ADC mfd cells to confgure their options in the shared config register.
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+ */
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+
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+#if 0
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+ int ingenic_adc_set_config(struct device *dev, uint32_t mask, uint32_t val);
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+#endif
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+
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+struct ingenic_adc_platform_data{
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+ //struct ingenic_battery_info battery_info;
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+ struct ingenic_ts_info ts_info;
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+};
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+
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+int adc_write_reg(struct device *dev,uint8_t addr_offset,uint32_t mask,uint32_t val);
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+uint32_t adc_read_reg(struct device *dev,uint8_t addr_offset);
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+#endif /*ingenic_adc.h*/
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