mirror of https://github.com/OpenIPC/firmware.git
				
				
				
			
		
			
				
	
	
		
			79 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			Diff
		
	
	
			
		
		
	
	
			79 lines
		
	
	
		
			2.6 KiB
		
	
	
	
		
			Diff
		
	
	
| diff -drupN a/include/dt-bindings/interrupt-controller/t40-irq.h b/include/dt-bindings/interrupt-controller/t40-irq.h
 | |
| --- a/include/dt-bindings/interrupt-controller/t40-irq.h	1970-01-01 03:00:00.000000000 +0300
 | |
| +++ b/include/dt-bindings/interrupt-controller/t40-irq.h	2022-06-09 05:02:35.000000000 +0300
 | |
| @@ -0,0 +1,74 @@
 | |
| +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_T40_IRQ_H
 | |
| +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_T40_IRQ_H
 | |
| +
 | |
| +#include <dt-bindings/interrupt-controller/mips-irq.h>
 | |
| +
 | |
| +#define IRQ_RESERVED0			(0)
 | |
| +#define IRQ_AIC0				(1)
 | |
| +#define IRQ_SYS_LEP	    		(2)   /* RISC-V */
 | |
| +#define IRQ_MIPI_DSI			(3)
 | |
| +#define IRQ_MIPI_RX_4L			(4)
 | |
| +#define IRQ_MIPI_RX_2L			(5)
 | |
| +#define IRQ_IPU			    	(6)
 | |
| +#define IRQ_SFC			    	(7)
 | |
| +#define IRQ_SSI1		    	(8)
 | |
| +#define IRQ_SSI0	    		(9)
 | |
| +#define IRQ_PDMA	    		(10)
 | |
| +#define IRQ_SSISLV	    		(11)
 | |
| +#define IRQ_DMIC	    		(12)
 | |
| +#define IRQ_RESERVED13			(13)
 | |
| +#define IRQ_GPIO3	    		(14)
 | |
| +#define IRQ_GPIO2		    	(15)
 | |
| +#define IRQ_GPIO1		    	(16)
 | |
| +#define IRQ_GPIO0		    	(17)
 | |
| +#define IRQ_GPIO_PORT(N) (IRQ_GPIO0 - (N))
 | |
| +#define IRQ_SADC	    		(18)
 | |
| +#define IRQ_RESERVED19			(19)
 | |
| +#define IRQ_LCD     			(20)
 | |
| +#define IRQ_OTG	        		(21)
 | |
| +#define IRQ_HASH	    		(22)
 | |
| +#define IRQ_AES	    			(23)
 | |
| +#define IRQ_RSA		    		(24)
 | |
| +#define IRQ_TCU2		    	(25)
 | |
| +#define IRQ_TCU1		    	(26)
 | |
| +#define IRQ_TCU0		    	(27)
 | |
| +#define IRQ_S2_VIC	    		(28)
 | |
| +#define IRQ_S1_VIC     			(29)
 | |
| +#define IRQ_S0_VIC	   			(30)
 | |
| +#define IRQ_ISP		    		(31)
 | |
| +
 | |
| +#define IRQ_RESERVED32    		(32 + 0)
 | |
| +#define IRQ_RESERVED33			(32 + 1)
 | |
| +#define IRQ_DTRNG	    		(32 + 2)
 | |
| +#define IRQ_RESERVED35			(32 + 3)
 | |
| +#define IRQ_MSC1	    		(32 + 4)
 | |
| +#define IRQ_MSC0		    	(32 + 5)
 | |
| +#define IRQ_RESERVED38			(32 + 6)
 | |
| +#define IRQ_BSCALER1			(32 + 7)
 | |
| +#define IRQ_BSCALER0			(32 + 8)
 | |
| +#define IRQ_DDR_DWU	    		(32 + 9)
 | |
| +#define IRQ_DRAW_BOX			(32 + 10)
 | |
| +#define IRQ_VO	        		(32 + 11)
 | |
| +#define IRQ_HARB2	    		(32 + 12)
 | |
| +#define IRQ_I2D     			(32 + 13)
 | |
| +#define IRQ_RESERVED46			(32 + 14)
 | |
| +#define IRQ_CPM	        		(32 + 15)
 | |
| +#define IRQ_UART3	    		(32 + 16)
 | |
| +#define IRQ_UART2	    		(32 + 17)
 | |
| +#define IRQ_UART1		    	(32 + 18)
 | |
| +#define IRQ_UART0		    	(32 + 19)
 | |
| +#define IRQ_DDR	    			(32 + 20)
 | |
| +#define IRQ_MON		        	(32 + 21)
 | |
| +#define IRQ_EFUSE	    		(32 + 22)
 | |
| +#define IRQ_GMAC0	    		(32 + 23)
 | |
| +#define IRQ_RESERVED56	    	(32 + 24)
 | |
| +#define IRQ_I2C3    			(32 + 25)
 | |
| +#define IRQ_I2C2	    		(32 + 26)
 | |
| +#define IRQ_I2C1	    		(32 + 27)
 | |
| +#define IRQ_I2C0	    		(32 + 28)
 | |
| +#define IRQ_PDMAM	    		(32 + 29)
 | |
| +#define IRQ_EL150	    		(32 + 30)
 | |
| +#define IRQ_RADIX    	    	(32 + 31)
 | |
| +
 | |
| +
 | |
| +#endif
 |