mirror of https://github.com/OpenIPC/firmware.git
124 lines
4.3 KiB
Diff
124 lines
4.3 KiB
Diff
diff -drupN a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
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--- a/arch/mips/mm/c-r4k.c 2017-10-21 18:09:07.000000000 +0300
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+++ b/arch/mips/mm/c-r4k.c 2022-06-09 05:02:27.000000000 +0300
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@@ -60,8 +60,10 @@ static inline void r4k_on_each_cpu(void
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* to restrict that call when a CM is not present because both
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* CM-based SMP protocols (CMP & CPS) restrict index-based cache ops.
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*/
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+#ifndef CONFIG_MACH_XBURST2
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if (!mips_cm_present())
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smp_call_function_many(&cpu_foreign_map, func, info, 1);
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+#endif
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func(info);
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preempt_enable();
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}
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@@ -378,9 +380,13 @@ static void r4k_blast_scache_page_setup(
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{
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unsigned long sc_lsize = cpu_scache_line_size();
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- if (scache_size == 0)
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+ if (scache_size == 0) {
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+#ifdef MIPS_BRIDGE_SYNC_WAR
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+ r4k_blast_scache_page = (void *)blast_inclusive_scache; /*CONFIG_MACH_XBURST*/
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+#else
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r4k_blast_scache_page = (void *)cache_noop;
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- else if (sc_lsize == 16)
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+#endif
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+ } else if (sc_lsize == 16)
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r4k_blast_scache_page = blast_scache16_page;
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else if (sc_lsize == 32)
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r4k_blast_scache_page = blast_scache32_page;
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@@ -396,9 +402,13 @@ static void r4k_blast_scache_page_indexe
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{
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unsigned long sc_lsize = cpu_scache_line_size();
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- if (scache_size == 0)
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+ if (scache_size == 0) {
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+#ifdef MIPS_BRIDGE_SYNC_WAR
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+ r4k_blast_scache_page_indexed = (void *)blast_inclusive_scache; /*CONFIG_MACH_XBURST*/
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+#else
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r4k_blast_scache_page_indexed = (void *)cache_noop;
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- else if (sc_lsize == 16)
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+#endif
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+ } else if (sc_lsize == 16)
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r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
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else if (sc_lsize == 32)
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r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
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@@ -414,9 +424,13 @@ static void r4k_blast_scache_setup(void)
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{
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unsigned long sc_lsize = cpu_scache_line_size();
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- if (scache_size == 0)
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+ if (scache_size == 0) {
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+#ifdef MIPS_BRIDGE_SYNC_WAR
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+ r4k_blast_scache = (void *)blast_inclusive_scache; /*CONFIG_MACH_XBURST*/
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+#else
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r4k_blast_scache = (void *)cache_noop;
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- else if (sc_lsize == 16)
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+#endif
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+ } else if (sc_lsize == 16)
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r4k_blast_scache = blast_scache16;
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else if (sc_lsize == 32)
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r4k_blast_scache = blast_scache32;
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@@ -770,7 +784,18 @@ static void r4k_dma_cache_inv(unsigned l
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if (cpu_has_safe_index_cacheops && size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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+#if defined(CONFIG_MACH_XBURST) || defined(CONFIG_MACH_XBURST2)
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+ unsigned long lsize = cpu_dcache_line_size();
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+ unsigned long cmask = (lsize - 1);
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+ unsigned long lmask = ~(cmask);
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+#endif
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R4600_HIT_CACHEOP_WAR_IMPL;
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+#if defined(CONFIG_MACH_XBURST) || defined(CONFIG_MACH_XBURST2)
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+ if (addr & cmask)
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+ cache_op(Hit_Writeback_Inv_D, addr & lmask);
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+ if ((addr + size) & cmask)
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+ cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & lmask);
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+#endif
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blast_inv_dcache_range(addr, addr + size);
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}
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preempt_enable();
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@@ -797,6 +822,10 @@ static void local_r4k_flush_cache_sigtra
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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protected_writeback_scache_line(addr & ~(sc_lsize - 1));
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+#ifdef MIPS_BRIDGE_SYNC_WAR
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+ else if (!cpu_icache_snoops_remote_store && MIPS_BRIDGE_SYNC_WAR) /*CONFIG_MACH_XBURST*/
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+ __fast_iob();
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+#endif
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if (ic_lsize)
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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if (MIPS4K_ICACHE_REFILL_WAR) {
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@@ -1487,6 +1516,9 @@ static void setup_scache(void)
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case CPU_LOONGSON3:
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loongson3_sc_init();
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return;
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+ case CPU_JZRISC:
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+ mips_sc_init();
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+ return;
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case CPU_CAVIUM_OCTEON3:
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case CPU_XLP:
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@@ -1497,7 +1529,7 @@ static void setup_scache(void)
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if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
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MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
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-#ifdef CONFIG_MIPS_CPU_SCACHE
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+#if defined(CONFIG_MIPS_CPU_SCACHE)
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if (mips_sc_init ()) {
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scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
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printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
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@@ -1590,7 +1622,10 @@ static void coherency_setup(void)
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if (cca < 0 || cca > 7)
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cca = read_c0_config() & CONF_CM_CMASK;
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_page_cachable_default = cca << _CACHE_SHIFT;
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-
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+#ifdef CONFIG_MACH_XBURST
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+ if (cca == CONF_CM_UNCACHED || cca == CONF_CM_CACHABLE_ACCELERATED)
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+ pr_warn("WARNNIGG: Using Uncacheable Kseg0\n");
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+#endif
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pr_debug("Using cache attribute %d\n", cca);
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change_c0_config(CONF_CM_CMASK, cca);
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