mirror of https://github.com/OpenIPC/firmware.git
135 lines
3.8 KiB
Diff
135 lines
3.8 KiB
Diff
diff -drupN a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
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--- a/arch/mips/kernel/cpu-probe.c 2017-10-21 18:09:07.000000000 +0300
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+++ b/arch/mips/kernel/cpu-probe.c 2022-06-09 05:02:27.000000000 +0300
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@@ -17,6 +17,7 @@
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/export.h>
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+#include <linux/kallsyms.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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@@ -414,6 +415,7 @@ static inline unsigned int decode_config
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config0 = read_c0_config();
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+
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/*
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* Look for Standard TLB or Dual VTLB and FTLB
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*/
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@@ -471,6 +473,8 @@ static inline unsigned int decode_config
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config1 = read_c0_config1();
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+ if (config1 & MIPS_CONF1_C2)
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+ c->ases |= MIPS_ASE_CU2;
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if (config1 & MIPS_CONF1_MD)
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c->ases |= MIPS_ASE_MDMX;
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if (config1 & MIPS_CONF1_WR)
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@@ -1332,18 +1336,65 @@ platform:
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}
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}
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+#ifdef CONFIG_XBURST_MXUV2
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+extern int soc_support_mxuv2(void);
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+#endif
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static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
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{
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+ unsigned int errorpc;
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+ static unsigned int showerrorpc[NR_CPUS];
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+ unsigned int config1;
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+
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+ if(showerrorpc[cpu] == 0) {
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+ __asm__ __volatile__ (
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+ "mfc0 %0, $30, 0 \n\t"
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+ "nop \n\t"
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+ :"=r"(errorpc)
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+ :);
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+
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+ printk("CPU%d RESET ERROR PC:%08X\n", cpu,errorpc);
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+ if(kernel_text_address(errorpc))
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+ print_ip_sym(errorpc);
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+ showerrorpc[cpu] = 1;
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+ }
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+
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decode_configs(c);
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/* JZRISC does not implement the CP0 counter. */
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+ /* INGENIC RISC does not implement the CP0 counter. */
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c->options &= ~MIPS_CPU_COUNTER;
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BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
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- switch (c->processor_id & PRID_IMP_MASK) {
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- case PRID_IMP_JZRISC:
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+
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+ switch (c->processor_id & PRID_IMP_PROCESSOR_ID_MSK) {
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+ case PRID_IMP_XBURST:
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+ {
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+ unsigned int config7;
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c->cputype = CPU_JZRISC;
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c->writecombine = _CACHE_UNCACHED_ACCELERATED;
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- __cpu_name[cpu] = "Ingenic JZRISC";
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+ __cpu_name[cpu] = "Xburst";
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+ /*
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+ * When CPU enters the long cycle, it will reduce the CPU speed to save power.
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+ * Set cp0 config7 bit 4 to disable this feature
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+ * This feature will cause bogoMips and loops_per_jiffy calculate in error
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+ */
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+ config7 = read_c0_config7();
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+ config7 |= (1 << 4);
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+ write_c0_config7(config7);
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+
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+ config1 = read_c0_config1();
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+#ifdef CONFIG_XBURST_MXUV2
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+ if(soc_support_mxuv2()) {
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+ c->ases |= MIPS_ASE_XBURSTMXUV2;
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+ } else
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+#endif
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+ //c->ases |= MIPS_ASE_XBURSTMXU;
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+ }
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+ break;
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+ case PRID_IMP_XBURST2:
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+ {
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+ c->cputype = CPU_JZRISC;
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+ __cpu_name[cpu] = "Ingenic XBurst@II";
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break;
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+ }
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default:
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panic("Unknown Ingenic Processor ID!");
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break;
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@@ -1444,6 +1495,7 @@ void cpu_probe(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int cpu = smp_processor_id();
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+ //unsigned long fpu_csr31 = 0;
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c->processor_id = PRID_IMP_UNKNOWN;
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c->fpu_id = FPIR_IMP_NONE;
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@@ -1482,6 +1534,7 @@ void cpu_probe(void)
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case PRID_COMP_INGENIC_D0:
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case PRID_COMP_INGENIC_D1:
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case PRID_COMP_INGENIC_E1:
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+ case PRID_COMP_INGENIC_13:
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cpu_probe_ingenic(c, cpu);
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break;
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case PRID_COMP_NETLOGIC:
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@@ -1512,7 +1565,20 @@ void cpu_probe(void)
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}
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if (c->options & MIPS_CPU_FPU)
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+ {
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+ //fpu_fcr31 = cpu_test_fpu_csr31(FPU_CSR_DEFAULT);
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cpu_set_fpu_opts(c);
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+ #if 0
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+ if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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+ MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
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+ if (c->fpu_id & MIPS_FPIR_3D)
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+ c->ases |= MIPS_ASE_MIPS3D;
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+ if (c->fpu_id & MIPS_FPIR_HAS2008)
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+ fpu_fcr31 = cpu_test_fpu_csr31(FPU_CSR_DEFAULT|FPU_CSR_MAC2008|FPU_CSR_ABS2008|FPU_CSR_NAN2008);
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+ }
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+ #endif
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+
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+ }
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else
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cpu_set_nofpu_opts(c);
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