mirror of https://github.com/OpenIPC/firmware.git
141 lines
5.9 KiB
Diff
141 lines
5.9 KiB
Diff
diff -drupN a/include/dt-bindings/clock/ingenic-t40.h b/include/dt-bindings/clock/ingenic-t40.h
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--- a/include/dt-bindings/clock/ingenic-t40.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/include/dt-bindings/clock/ingenic-t40.h 2022-06-09 05:02:35.000000000 +0300
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@@ -0,0 +1,136 @@
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+#ifndef _DT_BINDINGS_CLOCK_T40_H
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+#define _DT_BINDINGS_CLOCK_T40_H
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+
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+/* Fixed Clk */
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+#define CLK_ID_FIEXED 0
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+#define CLK_EXT (CLK_ID_FIEXED + 0)
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+#define CLK_RTC_EXT (CLK_ID_FIEXED + 1)
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+#define CLK_NR_FIXED (2)
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+
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+/* PLL clk */
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+#define CLK_ID_PLL (CLK_ID_FIEXED + CLK_NR_FIXED)
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+#define CLK_PLL_APLL (CLK_ID_PLL + 0)
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+#define CLK_PLL_MPLL (CLK_ID_PLL + 1)
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+#define CLK_PLL_VPLL (CLK_ID_PLL + 2)
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+#define CLK_PLL_EPLL (CLK_ID_PLL + 3)
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+#define CLK_NR_PLL (4)
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+
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+/* MUX clk */
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+#define CLK_ID_MUX (CLK_ID_PLL + CLK_NR_PLL)
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+#define CLK_MUX_SCLKA (CLK_ID_MUX + 0)
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+#define CLK_MUX_CPU_L2C (CLK_ID_MUX + 1)
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+#define CLK_MUX_AHB0 (CLK_ID_MUX + 2)
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+#define CLK_MUX_AHB2 (CLK_ID_MUX + 3)
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+#define CLK_MUX_PCLK (CLK_ID_MUX + 4)
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+#define CLK_MUX_DDR (CLK_ID_MUX + 5)
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+#define CLK_MUX_MACPHY (CLK_ID_MUX + 6)
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+#define CLK_MUX_LCD (CLK_ID_MUX + 7)
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+#define CLK_MUX_MSC0 (CLK_ID_MUX + 8)
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+#define CLK_MUX_MSC1 (CLK_ID_MUX + 9)
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+#define CLK_MUX_SFC (CLK_ID_MUX + 10)
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+#define CLK_MUX_SSI (CLK_ID_MUX + 11)
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+#define CLK_MUX_CIM0 (CLK_ID_MUX + 12)
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+#define CLK_MUX_CIM1 (CLK_ID_MUX + 13)
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+#define CLK_MUX_CIM2 (CLK_ID_MUX + 14)
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+#define CLK_MUX_ISP (CLK_ID_MUX + 15)
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+#define CLK_MUX_RSA (CLK_ID_MUX + 16)
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+#define CLK_MUX_EL150 (CLK_ID_MUX + 17)
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+#define CLK_MUX_I2ST (CLK_ID_MUX + 18)
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+#define CLK_MUX_I2SR (CLK_ID_MUX + 19)
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+#define CLK_MUX_BSCALER (CLK_ID_MUX + 20)
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+#define CLK_MUX_BT0 (CLK_ID_MUX + 21)
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+#define CLK_MUX_BT1 (CLK_ID_MUX + 22)
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+
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+#define CLK_NR_MUX (23)
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+
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+
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+#define CLK_ID_DIV (CLK_ID_MUX + CLK_NR_MUX)
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+#define CLK_DIV_DDR (CLK_ID_DIV + 0)
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+#define CLK_DIV_MACPHY (CLK_ID_DIV + 1)
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+#define CLK_DIV_LCD (CLK_ID_DIV + 2)
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+#define CLK_DIV_MSC0 (CLK_ID_DIV + 3)
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+#define CLK_DIV_MSC1 (CLK_ID_DIV + 4)
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+#define CLK_DIV_SFC (CLK_ID_DIV + 5)
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+#define CLK_DIV_SSI (CLK_ID_DIV + 6)
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+#define CLK_DIV_CIM0 (CLK_ID_DIV + 7)
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+#define CLK_DIV_CIM1 (CLK_ID_DIV + 8)
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+#define CLK_DIV_CIM2 (CLK_ID_DIV + 9)
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+#define CLK_DIV_ISP (CLK_ID_DIV + 10)
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+#define CLK_DIV_RSA (CLK_ID_DIV + 11)
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+#define CLK_DIV_EL150 (CLK_ID_DIV + 12)
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+#define CLK_DIV_I2ST (CLK_ID_DIV + 13)
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+#define CLK_DIV_I2SR (CLK_ID_DIV + 14)
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+#define CLK_DIV_BSCALER (CLK_ID_DIV + 15)
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+#define CLK_DIV_BT0 (CLK_ID_DIV + 16)
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+#define CLK_DIV_BT1 (CLK_ID_DIV + 17)
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+
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+#define CLK_DIV_CPU (CLK_ID_DIV + 18)
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+#define CLK_DIV_L2C (CLK_ID_DIV + 19)
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+#define CLK_DIV_AHB0 (CLK_ID_DIV + 20)
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+#define CLK_DIV_AHB2 (CLK_ID_DIV + 21)
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+#define CLK_DIV_APB (CLK_ID_DIV + 22)
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+#define CLK_DIV_CPU_L2C (CLK_ID_DIV + 23)
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+#define CLK_DIV_CPU_L2C_X1 (CLK_ID_DIV + 24)
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+#define CLK_DIV_CPU_L2C_X2 (CLK_ID_DIV + 25)
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+
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+#define CLK_NR_DIV (26)
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+
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+
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+/* Gate Clocks */
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+#define CLK_ID_GATE (CLK_ID_DIV + CLK_NR_DIV)
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+#define CLK_GATE_DDR (CLK_ID_GATE + 0)
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+#define CLK_GATE_TCU (CLK_ID_GATE + 1)
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+#define CLK_GATE_RESERVER29 (CLK_ID_GATE + 2)
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+#define CLK_GATE_DES (CLK_ID_GATE + 3)
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+#define CLK_GATE_RSA (CLK_ID_GATE + 4)
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+#define CLK_GATE_VO (CLK_ID_GATE + 5)
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+#define CLK_GATE_MIPI_CSI (CLK_ID_GATE + 6)
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+#define CLK_GATE_LCD (CLK_ID_GATE + 7)
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+#define CLK_GATE_ISP (CLK_ID_GATE + 8)
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+#define CLK_GATE_PDMA (CLK_ID_GATE + 9)
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+#define CLK_GATE_SFC (CLK_ID_GATE + 10)
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+#define CLK_GATE_SSI1 (CLK_ID_GATE + 11)
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+#define CLK_GATE_HASH (CLK_ID_GATE + 12)
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+#define CLK_GATE_SLV (CLK_ID_GATE + 13)
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+#define CLK_GATE_UART3 (CLK_ID_GATE + 14)
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+#define CLK_GATE_UART2 (CLK_ID_GATE + 15)
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+#define CLK_GATE_UART1 (CLK_ID_GATE + 16)
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+#define CLK_GATE_UART0 (CLK_ID_GATE + 17)
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+#define CLK_GATE_SADC (CLK_ID_GATE + 18)
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+#define CLK_GATE_DMIC (CLK_ID_GATE + 19)
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+#define CLK_GATE_AIC (CLK_ID_GATE + 20)
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+#define CLK_GATE_SMB3 (CLK_ID_GATE + 21)
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+#define CLK_GATE_SMB2 (CLK_ID_GATE + 22)
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+#define CLK_GATE_SMB1 (CLK_ID_GATE + 23)
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+#define CLK_GATE_SMB0 (CLK_ID_GATE + 24)
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+#define CLK_GATE_SSI0 (CLK_ID_GATE + 25)
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+#define CLK_GATE_MSC1 (CLK_ID_GATE + 26)
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+#define CLK_GATE_MSC0 (CLK_ID_GATE + 27)
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+#define CLK_GATE_OTG (CLK_ID_GATE + 28)
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+#define CLK_GATE_BSCALER (CLK_ID_GATE + 29)
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+#define CLK_GATE_EFUSE (CLK_ID_GATE + 30)
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+#define CLK_GATE_NEMC (CLK_ID_GATE + 31)
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+#define CLK_GATE_CPU (CLK_ID_GATE + 32)
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+#define CLK_GATE_APB0 (CLK_ID_GATE + 33)
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+#define CLK_GATE_RESERVER13 (CLK_ID_GATE + 34)
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+#define CLK_GATE_RESERVER12 (CLK_ID_GATE + 35)
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+#define CLK_GATE_OST (CLK_ID_GATE + 36)
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+#define CLK_GATE_AHB0 (CLK_ID_GATE + 37)
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+#define CLK_GATE_MONITOR (CLK_ID_GATE + 38)
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+#define CLK_GATE_I2D (CLK_ID_GATE + 39)
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+#define CLK_GATE_MIPI_DSI (CLK_ID_GATE + 40)
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+#define CLK_GATE_DRAWBOX (CLK_ID_GATE + 41)
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+#define CLK_GATE_AES (CLK_ID_GATE + 42)
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+#define CLK_GATE_GMAC (CLK_ID_GATE + 43)
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+#define CLK_GATE_AHB1 (CLK_ID_GATE + 44)
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+#define CLK_GATE_IPU (CLK_ID_GATE + 45)
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+#define CLK_GATE_DTRNG (CLK_ID_GATE + 46)
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+#define CLK_GATE_EL150 (CLK_ID_GATE + 47)
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+#define CLK_CE_I2ST (CLK_ID_GATE + 48)
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+#define CLK_CE_I2SR (CLK_ID_GATE + 49)
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+#define CLK_GATE_USBPHY (CLK_ID_GATE + 50)
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+#define CLK_NR_GATE (61)
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+#define CLK_ID_OTHER (CLK_ID_GATE + CLK_NR_GATE)
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+
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+#define NR_CLKS (CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_MUX + CLK_NR_DIV + CLK_NR_GATE)
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+#endif
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