mirror of https://github.com/OpenIPC/firmware.git
60 lines
1.2 KiB
Diff
60 lines
1.2 KiB
Diff
diff -drupN a/drivers/clk/ingenic/clk-pll.h b/drivers/clk/ingenic/clk-pll.h
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--- a/drivers/clk/ingenic/clk-pll.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/clk/ingenic/clk-pll.h 2022-06-09 05:02:28.000000000 +0300
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@@ -0,0 +1,55 @@
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+#ifndef __INGENIC_CLK_PLLV_H__
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+#define __INGENIC_CLK_PLLV_H__
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+
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+
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+extern const struct clk_ops ingenic_pll_ro_ops;
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+
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+#define PLL_RATE(_rate, _m, _n, _od1, _od0) \
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+{ \
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+ .rate = _rate, \
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+ .m = _m, \
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+ .n = _n, \
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+ .od1 = _od1, \
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+ .od0 = _od0, \
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+}
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+
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+struct ingenic_pll_rate_table {
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+ unsigned int rate;
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+ unsigned int m;
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+ unsigned int n;
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+ unsigned int od1;
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+ unsigned int od0;
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+};
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+
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+#define PLL_DESC(_regoff, _m, _m_w, _n, _n_w, _od1, _od1_w, _od0, _od0_w, _on, _en, _bs) \
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+{ \
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+ .regoff = _regoff, \
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+ .m_sft = _m, \
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+ .m_width = _m_w, \
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+ .n_sft = _n, \
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+ .n_width = _n_w, \
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+ .od1_sft = _od1, \
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+ .od1_width = _od1_w, \
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+ .od0_sft = _od0, \
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+ .od0_width = _od0_w, \
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+ .on_bit = _on, \
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+ .en_bit = _en, \
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+ .bs_bit = _bs, \
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+}
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+
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+struct ingenic_pll_hwdesc {
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+ u32 regoff;
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+ u8 m_sft;
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+ u8 m_width;
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+ u8 n_sft;
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+ u8 n_width;
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+ u8 od1_sft;
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+ u8 od1_width;
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+ u8 od0_sft;
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+ u8 od0_width;
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+ u8 on_bit;
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+ u8 en_bit;
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+ s8 bs_bit;
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+};
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+
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+#endif /*__INGENIC_CLK_PLLV1_H__*/
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