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firmware/br-ext-chip-hisilicon/board/hi3516cv100/kernel/patches/20_gpio_sysfs.patch

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diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bbb69e4..6956c1e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -953,6 +953,7 @@ config ARCH_HI3518
select HAVE_SCHED_CLOCK
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
+ select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_HAS_CPUFREQ
help
This enables support for Hisilicon hi3518 platform.
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c3ec52c..c81e1a5 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -21,6 +21,10 @@ GZFLAGS :=-9
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
KBUILD_CFLAGS +=$(call cc-option,-marm,)
+# Disable reading and writing of 16- and 32- bit values from address that
+# are not 16- or 32- bit aligned
+KBUILD_CFLAGS += $(call cc-option,-mno-unaligned-access)
+
# Never generate .eh_frame
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
diff --git a/arch/arm/mach-hi3518/core.c b/arch/arm/mach-hi3518/core.c
index 0196da1..ee31515 100644
--- a/arch/arm/mach-hi3518/core.c
+++ b/arch/arm/mach-hi3518/core.c
@@ -6,6 +6,7 @@
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
+#include <linux/amba/pl061.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cnt32_to_63.h>
@@ -347,19 +348,115 @@ struct sys_timer hi3518_timer = {
}, \
.res = { \
.start = base##_BASE, \
- .end = base##_BASE + 0x10000 - 1, \
+ .end = base##_BASE + 0x1000 - 1, \
.flags = IORESOURCE_IO, \
}, \
.dma_mask = ~0, \
.irq = { base##_IRQ, NO_IRQ } \
}
-HIL_AMBA_DEVICE(uart0, "uart:0", UART0, NULL);
-HIL_AMBA_DEVICE(uart1, "uart:1", UART1, NULL);
+#if defined(CONFIG_GPIO_PL061) || defined(CONFIG_GPIO_PL061_MODULE)
+static struct pl061_platform_data gpio0_plat_data = {
+ .gpio_base = 0,
+ .irq_base = GPIO0_IRQ_START,
+};
+
+static struct pl061_platform_data gpio1_plat_data = {
+ .gpio_base = 8,
+ .irq_base = GPIO1_IRQ_START,
+};
+
+static struct pl061_platform_data gpio2_plat_data = {
+ .gpio_base = 16,
+ .irq_base = GPIO2_IRQ_START,
+};
+
+static struct pl061_platform_data gpio3_plat_data = {
+ .gpio_base = 24,
+ .irq_base = GPIO3_IRQ_START,
+};
+
+static struct pl061_platform_data gpio4_plat_data = {
+ .gpio_base = 32,
+ .irq_base = GPIO4_IRQ_START,
+};
+
+static struct pl061_platform_data gpio5_plat_data = {
+ .gpio_base = 40,
+ .irq_base = GPIO5_IRQ_START,
+};
+
+static struct pl061_platform_data gpio6_plat_data = {
+ .gpio_base = 48,
+ .irq_base = GPIO6_IRQ_START,
+};
+
+static struct pl061_platform_data gpio7_plat_data = {
+ .gpio_base = 56,
+ .irq_base = GPIO7_IRQ_START,
+};
+
+static struct pl061_platform_data gpio8_plat_data = {
+ .gpio_base = 64,
+ .irq_base = GPIO8_IRQ_START,
+};
+
+static struct pl061_platform_data gpio9_plat_data = {
+ .gpio_base = 72,
+ .irq_base = GPIO9_IRQ_START,
+};
+
+static struct pl061_platform_data gpio10_plat_data = {
+ .gpio_base = 80,
+ .irq_base = GPIO10_IRQ_START,
+};
+
+static struct pl061_platform_data gpio11_plat_data = {
+ .gpio_base = 88,
+ .irq_base = GPIO11_IRQ_START,
+};
+#endif
+
+HIL_AMBA_DEVICE(uart0, "uart:0", UART0, NULL);
+HIL_AMBA_DEVICE(uart1, "uart:1", UART1, NULL);
+#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
+HIL_AMBA_DEVICE(wdog, "dev:wdog", WDG, NULL);
+#endif
+#if defined(CONFIG_GPIO_PL061) || defined(CONFIG_GPIO_PL061_MODULE)
+HIL_AMBA_DEVICE(gpio0, "dev:gpio0", GPIO0, &gpio0_plat_data);
+HIL_AMBA_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
+HIL_AMBA_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
+HIL_AMBA_DEVICE(gpio3, "dev:gpio3", GPIO3, &gpio3_plat_data);
+HIL_AMBA_DEVICE(gpio4, "dev:gpio4", GPIO4, &gpio4_plat_data);
+HIL_AMBA_DEVICE(gpio5, "dev:gpio5", GPIO5, &gpio5_plat_data);
+HIL_AMBA_DEVICE(gpio6, "dev:gpio6", GPIO6, &gpio6_plat_data);
+HIL_AMBA_DEVICE(gpio7, "dev:gpio7", GPIO7, &gpio7_plat_data);
+HIL_AMBA_DEVICE(gpio8, "dev:gpio8", GPIO8, &gpio8_plat_data);
+HIL_AMBA_DEVICE(gpio9, "dev:gpio9", GPIO9, &gpio9_plat_data);
+HIL_AMBA_DEVICE(gpio10, "dev:gpio10", GPIO10, &gpio10_plat_data);
+HIL_AMBA_DEVICE(gpio11, "dev:gpio11", GPIO11, &gpio11_plat_data);
+#endif
static struct amba_device *amba_devs[] __initdata = {
&HIL_AMBADEV_NAME(uart0),
&HIL_AMBADEV_NAME(uart1),
+#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
+ &HIL_AMBADEV_NAME(wdog),
+#endif
+#if defined(CONFIG_GPIO_PL061) || defined(CONFIG_GPIO_PL061_MODULE)
+ &HIL_AMBADEV_NAME(gpio0),
+ &HIL_AMBADEV_NAME(gpio1),
+ &HIL_AMBADEV_NAME(gpio2),
+ &HIL_AMBADEV_NAME(gpio3),
+ &HIL_AMBADEV_NAME(gpio4),
+ &HIL_AMBADEV_NAME(gpio5),
+ &HIL_AMBADEV_NAME(gpio6),
+ &HIL_AMBADEV_NAME(gpio7),
+ &HIL_AMBADEV_NAME(gpio8),
+ &HIL_AMBADEV_NAME(gpio9),
+ &HIL_AMBADEV_NAME(gpio10),
+ &HIL_AMBADEV_NAME(gpio11),
+#endif
};
/*
@@ -369,6 +466,18 @@ static struct clk uart_clk = {
.rate = 3000000,
};
+#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
+static struct clk wdog_clk = {
+ .rate = 3000000,
+};
+#endif
+
+#if defined(CONFIG_GPIO_PL061) || defined(CONFIG_GPIO_PL061_MODULE)
+static struct clk gpio_clk = {
+ .rate = CONFIG_DEFAULT_BUSCLK,
+};
+#endif
+
static struct clk_lookup lookups[] = {
{ /* UART0 */
.dev_id = "uart:0",
@@ -378,6 +487,62 @@ static struct clk_lookup lookups[] = {
.dev_id = "uart:1",
.clk = &uart_clk,
},
+#if defined(CONFIG_ARM_SP805_WATCHDOG) || defined(CONFIG_ARM_SP805_WATCHDOG_MODULE)
+ { /* WDOG */
+ .dev_id = "dev:wdog",
+ .clk = &wdog_clk,
+ },
+#endif
+#if defined(CONFIG_GPIO_PL061) || defined(CONFIG_GPIO_PL061_MODULE)
+ { /* GPIO0 */
+ .dev_id = "dev:gpio0",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO1 */
+ .dev_id = "dev:gpio1",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO2 */
+ .dev_id = "dev:gpio2",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO3 */
+ .dev_id = "dev:gpio3",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO4 */
+ .dev_id = "dev:gpio4",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO5 */
+ .dev_id = "dev:gpio5",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO6 */
+ .dev_id = "dev:gpio6",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO7 */
+ .dev_id = "dev:gpio7",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO8 */
+ .dev_id = "dev:gpio8",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO9 */
+ .dev_id = "dev:gpio9",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO10 */
+ .dev_id = "dev:gpio10",
+ .clk = &gpio_clk,
+ },
+ { /* GPIO11 */
+ .dev_id = "dev:gpio11",
+ .clk = &gpio_clk,
+ },
+#endif
};
void __init hi3518_init(void)
diff --git a/arch/arm/mach-hi3518/include/mach/irqs.h b/arch/arm/mach-hi3518/include/mach/irqs.h
index d1c9b09..3d6a2f2 100644
--- a/arch/arm/mach-hi3518/include/mach/irqs.h
+++ b/arch/arm/mach-hi3518/include/mach/irqs.h
@@ -3,12 +3,52 @@
#define HI3518_IRQ_START (0)
+#define WDG_IRQ (HI3518_IRQ_START + 1)
+#define RTC_IRQ (HI3518_IRQ_START + 2)
#define TIMER01_IRQ (HI3518_IRQ_START + 3)
#define TIMER23_IRQ (HI3518_IRQ_START + 4)
#define UART0_IRQ (HI3518_IRQ_START + 5)
#define UART1_IRQ (HI3518_IRQ_START + 5)
+#define DMAC_IRQ (HI3518_IRQ_START + 14)
#define UART2_IRQ (HI3518_IRQ_START + 25)
+#define GPIO0_IRQ (HI3518_IRQ_START + 29)
+#define GPIO1_IRQ (HI3518_IRQ_START + 29)
+#define GPIO2_IRQ (HI3518_IRQ_START + 29)
+#define GPIO3_IRQ (HI3518_IRQ_START + 30)
+#define GPIO4_IRQ (HI3518_IRQ_START + 30)
+#define GPIO5_IRQ (HI3518_IRQ_START + 30)
+#define GPIO6_IRQ (HI3518_IRQ_START + 31)
+#define GPIO7_IRQ (HI3518_IRQ_START + 31)
+#define GPIO8_IRQ (HI3518_IRQ_START + 31)
+#define GPIO9_IRQ (HI3518_IRQ_START + 31)
+#define GPIO10_IRQ (HI3518_IRQ_START + 30)
+#define GPIO11_IRQ (HI3518_IRQ_START + 29)
-#define NR_IRQS (HI3518_IRQ_START + 32)
+#define GPIO0_IRQ_START (HI3518_IRQ_START + 32)
+#define GPIO0_IRQ_END (GPIO0_IRQ_START + 7)
+#define GPIO1_IRQ_START (GPIO0_IRQ_END + 1)
+#define GPIO1_IRQ_END (GPIO1_IRQ_START + 7)
+#define GPIO2_IRQ_START (GPIO1_IRQ_END + 1)
+#define GPIO2_IRQ_END (GPIO2_IRQ_START + 7)
+#define GPIO3_IRQ_START (GPIO2_IRQ_END + 1)
+#define GPIO3_IRQ_END (GPIO3_IRQ_START + 7)
+#define GPIO4_IRQ_START (GPIO3_IRQ_END + 1)
+#define GPIO4_IRQ_END (GPIO4_IRQ_START + 7)
+#define GPIO5_IRQ_START (GPIO4_IRQ_END + 1)
+#define GPIO5_IRQ_END (GPIO5_IRQ_START + 7)
+#define GPIO6_IRQ_START (GPIO5_IRQ_END + 1)
+#define GPIO6_IRQ_END (GPIO6_IRQ_START + 7)
+#define GPIO7_IRQ_START (GPIO6_IRQ_END + 1)
+#define GPIO7_IRQ_END (GPIO7_IRQ_START + 7)
+#define GPIO8_IRQ_START (GPIO7_IRQ_END + 1)
+#define GPIO8_IRQ_END (GPIO8_IRQ_START + 7)
+#define GPIO9_IRQ_START (GPIO8_IRQ_END + 1)
+#define GPIO9_IRQ_END (GPIO9_IRQ_START + 7)
+#define GPIO10_IRQ_START (GPIO9_IRQ_END + 1)
+#define GPIO10_IRQ_END (GPIO10_IRQ_START + 7)
+#define GPIO11_IRQ_START (GPIO10_IRQ_END + 1)
+#define GPIO11_IRQ_END (GPIO11_IRQ_START + 7)
+
+#define NR_IRQS (GPIO11_IRQ_END + 1)
#endif
diff --git a/arch/arm/mach-hi3518/include/mach/platform.h b/arch/arm/mach-hi3518/include/mach/platform.h
index 45ae3df..227a9c7 100644
--- a/arch/arm/mach-hi3518/include/mach/platform.h
+++ b/arch/arm/mach-hi3518/include/mach/platform.h
@@ -4,6 +4,18 @@
#include <mach/io.h>
#define DDR_BASE 0x80000000
+#define GPIO11_BASE 0x201F0000
+#define GPIO10_BASE 0x201E0000
+#define GPIO9_BASE 0x201D0000
+#define GPIO8_BASE 0x201C0000
+#define GPIO7_BASE 0x201B0000
+#define GPIO6_BASE 0x201A0000
+#define GPIO5_BASE 0x20190000
+#define GPIO4_BASE 0x20180000
+#define GPIO3_BASE 0x20170000
+#define GPIO2_BASE 0x20160000
+#define GPIO1_BASE 0x20150000
+#define GPIO0_BASE 0x20140000
#define DDRC_BASE 0x20110000
#define IOCONFIG_BASE 0x200F0000
#define UART2_BASE 0x200A0000
--- a/arch/arm/mach-hi3518/include/mach/gpio.h
+++ b/arch/arm/mach-hi3518/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
+#define gpio_to_irq __gpio_to_irq
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