mirror of https://github.com/OpenIPC/firmware.git
629 lines
15 KiB
Diff
629 lines
15 KiB
Diff
--- linux-4.9.37/arch/arm/boot/dts/gk7202v300.dtsi 1970-01-01 03:00:00.000000000 +0300
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+++ linux-4.9.y/arch/arm/boot/dts/gk7202v300.dtsi 2021-06-07 13:01:32.000000000 +0300
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@@ -0,0 +1,625 @@
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+/*
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+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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+ */
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+#include "skeleton.dtsi"
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+#include <dt-bindings/clock/gk7202v300-clock.h>
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+/ {
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+ aliases {
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+ serial0 = &uart0;
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+ serial1 = &uart1;
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+ serial2 = &uart2;
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+ i2c0 = &i2c_bus0;
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+ i2c1 = &i2c_bus1;
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+ i2c2 = &i2c_bus2;
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+ spi0 = &spi_bus0;
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+ spi1 = &spi_bus1;
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+ gpio0 = &gpio_chip0;
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+ gpio1 = &gpio_chip1;
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+ gpio2 = &gpio_chip2;
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+ gpio4 = &gpio_chip4;
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+ gpio5 = &gpio_chip5;
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+ gpio6 = &gpio_chip6;
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+ gpio7 = &gpio_chip7;
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+ gpio8 = &gpio_chip8;
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+ };
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+
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+ cpus {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ enable-method = "goke,gk7202v300";
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+
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+ cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ clock-frequency = <GK7202V300_FIXED_1000M>;
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+ reg = <0>;
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+ };
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+ };
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+
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+ pmu {
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+ compatible = "arm,armv7-pmu";
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+ interrupts = <0 58 4>;
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+ };
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+
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+ clock: clock@12010000 {
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+ compatible = "goke,gk7202v300-clock", "syscon";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ #clock-cells = <1>;
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+ #reset-cells = <2>;
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+ reg = <0x12010000 0x1000>;
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+ };
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+
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+ gic: interrupt-controller@10300000 {
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+ compatible = "arm,cortex-a7-gic";
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+ #interrupt-cells = <3>;
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+ #address-cells = <0>;
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+ interrupt-controller;
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+ /* gic dist base, gic cpu base , no virtual support */
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+ reg = <0x10301000 0x1000>, <0x10302000 0x100>;
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+ };
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+
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+ syscounter {
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+ compatible = "arm,armv7-timer";
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+ interrupt-parent = <&gic>;
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+ interrupts = <1 13 0xf08>,
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+ <1 14 0xf08>;
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+ clock-frequency = <50000000>;
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+ };
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+
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+ soc {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "simple-bus";
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+ interrupt-parent = <&gic>;
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+ ranges;
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+
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+ clk_3m: clk_3m {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <3000000>;
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+ };
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+
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+ clk_apb: clk_apb {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <50000000>;
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+ };
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+
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+ pmu {
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+ compatible = "arm,cortex-a7-pmu";
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+ interrupts = <0 58 4>;
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+ };
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+
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+ sysctrl: system-controller@12020000 {
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+ compatible = "goke,sysctrl";
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+ reg = <0x12020000 0x1000>;
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+ reboot-offset = <0x4>;
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+ #clock-cells = <1>;
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+ };
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+
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+ iocfg_ctrl: iocfg-controller@100c0000 {
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+ compatible = "syscon";
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+ reg = <0x100C0000 0x10000>;
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+ };
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+
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+ iocfg_ctrl2: iocfg-controller2@112c0000 {
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+ compatible = "syscon";
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+ reg = <0x112C0000 0x10000>;
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+ };
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+
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+#ifdef CONFIG_EDMAC
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+ edmac: edma-controller@100B0000 {
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+ compatible = "goke,edmac";
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+ reg = <0x100B0000 0x1000>;
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+ interrupts = <0 38 4>;
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+ clocks = <&clock GK7202V300_EDMAC_CLK>, <&clock GK7202V300_EDMAC_AXICLK>;
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+ clock-names = "apb_pclk", "axi_aclk";
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+ clock-cells = <2>;
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+ resets = <&clock 0x194 0>;
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+ reset-names = "dma-reset";
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+ dma-requests = <32>;
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+ dma-channels = <4>;
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+ devid = <0>;
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+ #dma-cells = <2>;
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+ status = "okay";
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+ };
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+#endif
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+ amba {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "arm,amba-bus";
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+ ranges;
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+
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+ dual_timer0: dual_timer@12000000 {
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+ compatible = "arm,sp804", "arm,primecell";
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+ /* timer0 & timer1 */
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+ interrupts = <0 5 4>;
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+ reg = <0x12000000 0x1000>;
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+ clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
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+ clock-names = "timer00", "timer01", "apb_pclk";
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+ status = "disabled";
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+ };
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+
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+ dual_timer1: dual_timer@12001000 {
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+ compatible = "arm,sp804", "arm,primecell";
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+ /* timer2 & timer3 */
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+ interrupts = <0 6 4>;
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+ reg = <0x12001000 0x1000>;
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+ clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
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+ clock-names = "timer10", "timer11", "apb_pclk";
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+ status = "disabled";
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+ };
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+
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+ uart0: uart@12040000 {
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+ compatible = "arm,pl011", "arm,primecell";
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+ reg = <0x12040000 0x1000>;
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+ interrupts = <0 7 4>;
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+ clocks = <&clock GK7202V300_UART0_CLK>;
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+ clock-names = "apb_pclk";
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+ status = "disabled";
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+ };
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+
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+ uart1: uart@12041000 {
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+ compatible = "arm,pl011", "arm,primecell";
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+ reg = <0x12041000 0x1000>;
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+ interrupts = <0 8 4>;
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+ clocks = <&clock GK7202V300_UART1_CLK>;
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+ clock-names = "apb_pclk";
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+#ifdef CONFIG_EDMAC
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+ dmas = <&edmac 19 19>, <&edmac 18 18>;
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+ dma-names = "tx","rx";
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+#endif
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+ status = "disabled";
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+ };
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+
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+ uart2: uart@12042000 {
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+ compatible = "arm,pl011", "arm,primecell";
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+ reg = <0x12042000 0x1000>;
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+ interrupts = <0 9 4>;
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+ clocks = <&clock GK7202V300_UART2_CLK>;
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+ clock-names = "apb_pclk";
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+#ifdef CONFIG_EDMAC
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+ dmas = <&edmac 21 21>, <&edmac 20 20>;
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+ dma-names = "tx","rx";
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+#endif
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+ status = "disabled";
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+ };
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+ };
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+
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+ i2c_bus0: i2c@12060000 {
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+ compatible = "goke,goke-i2c";
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+ reg = <0x12060000 0x1000>;
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+ clocks = <&clock GK7202V300_I2C0_CLK>;
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+ status = "disabled";
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+ };
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+
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+ i2c_bus1: i2c@12061000 {
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+ compatible = "goke,goke-i2c";
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+ reg = <0x12061000 0x1000>;
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+ clocks = <&clock GK7202V300_I2C1_CLK>;
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+ status = "disabled";
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+ };
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+
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+ i2c_bus2: i2c@12062000 {
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+ compatible = "goke,goke-i2c";
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+ reg = <0x12062000 0x1000>;
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+ clocks = <&clock GK7202V300_I2C2_CLK>;
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+ status = "disabled";
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+ };
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+
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+ spi_bus0: spi@12070000 {
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+ compatible = "arm,pl022", "arm,primecell";
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+ arm,primecell-periphid = <0x00041022>;
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+ reg = <0x12070000 0x1000>;
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+ interrupts = <0 14 4>;
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+ clocks = <&clock GK7202V300_SPI0_CLK>;
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+ clock-names = "apb_pclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+#ifdef CONFIG_EDMAC
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+ dmas = <&edmac 27 27>, <&edmac 26 26>;
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+ dma-names = "tx","rx";
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+#endif
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+ status = "disabled";
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+ };
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+
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+ spi_bus1: spi@12071000 {
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+ compatible = "arm,pl022", "arm,primecell";
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+ arm,primecell-periphid = <0x00041022>;
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+ reg = <0x12071000 0x1000>, <0x12028000 0x4>;
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+ interrupts = <0 15 4>;
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+ clocks = <&clock GK7202V300_SPI1_CLK>;
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+ clock-names = "apb_pclk";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ num-cs = <2>;
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+ spi_cs_sb = <2>;
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+ spi_cs_mask_bit = <0x4>;//0100
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+#ifdef CONFIG_EDMAC
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+ dmas = <&edmac 29 29>, <&edmac 28 28>;
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+ dma-names = "tx","rx";
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+#endif
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+ status = "disabled";
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+ };
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+
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+ mdio0: mdio@10041100 {
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+ compatible = "goke,femac-mdio";
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+ reg = <0x10041100 0x10>,<0x12028024 0x4>;
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+ clocks = <&clock GK7202V300_ETH0_CLK>;
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+ clock-names = "mdio";
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+ resets = <&clock 0x16c 3>;
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+ reset-names = "internal-phy";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ femac: ethernet@10040000 {
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+ compatible = "goke,femac";
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+ reg = <0x10040000 0x1000>,<0x10041300 0x200>;
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+ interrupts = <0 33 4>;
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+ clocks = <&clock GK7202V300_ETH0_CLK>;
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+ resets = <&clock 0x16c 0>;
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+ reset-names = "mac";
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+ };
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+
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+ fmc: flash-memory-controller@10000000 {
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+ compatible = "goke,fmc";
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+ reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
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+ reg-names = "control", "memory";
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+ clocks = <&clock GK7202V300_FMC_CLK>;
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+ max-dma-size = <0x2000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ sfc:spi-nor@0 {
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+ compatible = "goke,fmc-spi-nor";
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+ assigned-clocks = <&clock GK7202V300_FMC_CLK>;
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+ assigned-clock-rates = <24000000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ snfc:spi-nand@0 {
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+ compatible = "goke,fmc-spi-nand";
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+ assigned-clocks = <&clock GK7202V300_FMC_CLK>;
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+ assigned-clock-rates = <24000000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+
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+ mmc0: sdhci@0x10010000 {
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+ compatible = "goke,sdhci";
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+ reg = <0x10010000 0x1000>;
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+ interrupts = <0 30 4>;
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+ clocks = <&clock GK7202V300_MMC0_CLK>;
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+ clock-names = "mmc_clk";
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+ resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
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+ reset-names = "crg_reset", "dll_reset";
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+ max-frequency = <150000000>;
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+ crg_regmap = <&clock>;
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+ iocfg_regmap = <&iocfg_ctrl>;
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+ bus-width = <4>;
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+ cap-mmc-highspeed;
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+ cap-mmc-hw-reset;
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+ cap-sd-highspeed;
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+ mmc-hs200-1_8v;
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+ full-pwr-cycle;
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+ devid = <0>;
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+ status = "enable";
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+ };
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+
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+ mmc1: sdhci@0x10020000 {
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+ compatible = "goke,sdhci";
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+ reg = <0x10020000 0x1000>;
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+ interrupts = <0 31 4>;
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+ clocks = <&clock GK7202V300_MMC1_CLK>;
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+ clock-names = "mmc_clk";
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+ resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
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+ reset-names = "crg_reset", "dll_reset";
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+ max-frequency = <50000000>;
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+ crg_regmap = <&clock>;
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+ iocfg_regmap = <&iocfg_ctrl2>;
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+ bus-width = <4>;
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+ cap-sd-highspeed;
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+ full-pwr-cycle;
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+ devid = <2>;
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+ status = "enable";
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+ };
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+
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+ usb2_phy0: phy2-0 {
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+ compatible = "goke,usbp2-phy";
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+ reg = <0x100D0000 0x1000>,
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+ <0x12010000 0x1000>,
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+ <0x100c0000 0x1000>;
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+ clocks = <&clock GK7202V300_USB2_PHY_APB_CLK>,
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+ <&clock GK7202V300_USB2_PHY_PLL_CLK>,
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+ <&clock GK7202V300_USB2_PHY_XO_CLK>;
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+ clock-names = "clk_u2phy_apb_ref",
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+ "clk_u2phy_pll_ref",
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+ "clk_u2phy_xo_ref";
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+ resets = <&clock 0x140 0>,
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+ <&clock 0x140 1>;
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+ reset-names = "phy_por_reset",
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+ "phy_tpor_reset";
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+ phy_pll_offset = <0x14>;
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+ phy_pll_mask = <0x03>;
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+ phy_pll_val = <0x00>;
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+ crg_offset = <0x140>;
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+ crg_defal_mask = <0x0c07>;
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+ crg_defal_val = <0x0807>;
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+ vbus_offset = <0x7c>;
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+ vbus_val = <0x0531>;
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+ pwren_offset = <0x80>;
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+ pwren_val = <0x1>;
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+ ana_cfg_0_eye_val = <0x0433cc23>;
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+ ana_cfg_0_offset = <0x00>;
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+ ana_cfg_2_eye_val = <0x00320f0f>;
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+ ana_cfg_2_offset = <0x08>;
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+ ana_cfg_4_eye_val = <0x655>;
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+ ana_cfg_4_offset = <0x10>;
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+ trim_otp_addr = <0x12028004>;
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+ trim_otp_mask = <0x1f>;
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+ trim_otp_bit_offset = <0x00>;
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+ trim_otp_min = <0x09>;
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+ trim_otp_max = <0x1d>;
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+ #phy-cells = <0>;
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+ };
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+
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+ usbdrd3_0: usb3-0{
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+ compatible = "goke,dwusb2";
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+ reg = <0x10030000 0x10000>,
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+ <0x12010000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ crg_offset = <0x140>;
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+ crg_ctrl_def_mask = <0x3308>;
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+ crg_ctrl_def_val = <0x1308>;
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+ clocks = <&clock GK7202V300_USB2_BUS_CLK>,
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+ <&clock GK7202V300_USB2_REF_CLK>,
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+ <&clock GK7202V300_USB2_UTMI_CLK>;
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+ clock-names = "usb2_bus_clk",
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+ "usb2_ref_clk",
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+ "usb2_utmi_clk";
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+ resets = <&clock 0x140 3>;
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+ reset-names = "vcc_reset";
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+ ranges;
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+
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+ dwc3@0x100e0000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x10030000 0x10000>;
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+ interrupts = <0 39 4>;
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+ interrupt-names = "peripheral";
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+ phys = <&usb2_phy0>;
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+ phy-names = "usb2-phy";
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+ maximum-speed = "high-speed";
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+ dr_mode = "peripheral";
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+ eps_directions = <0x6a>;
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+ snps,eps_new_init;
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+ eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
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+ snps,usb2-lpm-disable;
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+ };
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+ };
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+
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+ gpio_chip0: gpio_chip@120b0000 {
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+ compatible = "arm,pl061", "arm,primecell";
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+ reg = <0x120b0000 0x1000>;
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+ interrupts = <0 16 4>;
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+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
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+ clock-names = "apb_pclk";
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+ #gpio-cells = <2>;
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+ status = "disabled";
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+ };
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+
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+ gpio_chip1: gpio_chip@120b1000 {
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+ compatible = "arm,pl061", "arm,primecell";
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+ reg = <0x120b1000 0x1000>;
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+ interrupts = <0 17 4>;
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+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
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+ clock-names = "apb_pclk";
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+ #gpio-cells = <2>;
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+ status = "disabled";
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+ };
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+
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+ gpio_chip2: gpio_chip@120b2000 {
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+ compatible = "arm,pl061", "arm,primecell";
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+ reg = <0x120b2000 0x1000>;
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+ interrupts = <0 18 4>;
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+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
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+ clock-names = "apb_pclk";
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+ #gpio-cells = <2>;
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+ status = "disabled";
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+ };
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+
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+ gpio_chip4: gpio_chip@120b4000 {
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+ compatible = "arm,pl061", "arm,primecell";
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+ reg = <0x120b4000 0x1000>;
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+ interrupts = <0 20 4>;
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+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
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+ clock-names = "apb_pclk";
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+ #gpio-cells = <2>;
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+ status = "disabled";
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+ };
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+
|
|
+ gpio_chip5: gpio_chip@120b5000 {
|
|
+ compatible = "arm,pl061", "arm,primecell";
|
|
+ reg = <0x120b5000 0x1000>;
|
|
+ interrupts = <0 21 4>;
|
|
+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #gpio-cells = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpio_chip6: gpio_chip@120b6000 {
|
|
+ compatible = "arm,pl061", "arm,primecell";
|
|
+ reg = <0x120b6000 0x1000>;
|
|
+ interrupts = <0 22 4>;
|
|
+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #gpio-cells = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpio_chip7: gpio_chip@120b7000 {
|
|
+ compatible = "arm,pl061", "arm,primecell";
|
|
+ reg = <0x120b7000 0x1000>;
|
|
+ interrupts = <0 23 4>;
|
|
+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #gpio-cells = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ gpio_chip8: gpio_chip@120b8000 {
|
|
+ compatible = "arm,pl061", "arm,primecell";
|
|
+ reg = <0x120b8000 0x1000>;
|
|
+ interrupts = <0 24 4>;
|
|
+ clocks = <&clock GK7202V300_SYSAPB_CLK>;
|
|
+ clock-names = "apb_pclk";
|
|
+ #gpio-cells = <2>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ rtc: rtc@120e0000 {
|
|
+ compatible = "goke,rtc";
|
|
+ reg = <0x120e0000 0x1000>;
|
|
+ interrupts = <0 0 4>;
|
|
+ };
|
|
+
|
|
+ cipher: cipher@0x10050000 {
|
|
+ compatible = "goke,cipher";
|
|
+ reg = <0x10050000 0x10000>;
|
|
+ reg-names = "cipher";
|
|
+ interrupts = <0 34 4>, <0 34 4>;
|
|
+ interrupt-names = "cipher", "hash";
|
|
+ };
|
|
+
|
|
+ adc: adc@120a0000 {
|
|
+ compatible = "goke,lsadc";
|
|
+ reg = <0x120a0000 0x1000>;
|
|
+ interrupts = <0 4 4>;
|
|
+ interrupt-names = "adc";
|
|
+ resets = <&clock 0x1bc 2>;
|
|
+ reset-names = "lsadc-crg";
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
+ wdg: wdg@0x12030000 {
|
|
+ compatible = "goke,wdg";
|
|
+ reg = <0x12030000 0x1000>;
|
|
+ reg-names = "wdg";
|
|
+ interrupts = <0 2 4>;
|
|
+ interrupt-names = "wdg";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ media {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ compatible = "simple-bus";
|
|
+ interrupt-parent = <&gic>;
|
|
+ ranges;
|
|
+
|
|
+ osal: osal {
|
|
+ compatible = "goke,osal";
|
|
+ };
|
|
+
|
|
+ sys: sys@12010000 {
|
|
+ compatible = "goke,sys";
|
|
+ };
|
|
+
|
|
+ mipi: mipi@0x11240000 {
|
|
+ compatible = "goke,mipi";
|
|
+ reg = <0x11240000 0x10000>;
|
|
+ reg-names = "mipi_rx";
|
|
+ interrupts = <0 45 4>;
|
|
+ interrupt-names = "mipi_rx";
|
|
+ };
|
|
+
|
|
+ vi: vi@11000000 {
|
|
+ compatible = "goke,vi";
|
|
+ reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
|
|
+ reg-names = "VI_CAP0", "VI_PROC0";
|
|
+ interrupts = <0 43 4>, <0 44 4>;
|
|
+ interrupt-names = "VI_CAP0", "VI_PROC0";
|
|
+ };
|
|
+
|
|
+ isp: isp@11220000 {
|
|
+ compatible = "goke,isp";
|
|
+ reg = <0x11220000 0x20000>;
|
|
+ reg-names = "ISP";
|
|
+ interrupts = <0 43 4>;
|
|
+ interrupt-names = "ISP";
|
|
+ };
|
|
+
|
|
+ vpss: vpss@11400000 {
|
|
+ compatible = "goke,vpss";
|
|
+ reg = <0x11400000 0x10000>;
|
|
+ reg-names = "vpss0";
|
|
+ interrupts = <0 46 4>;
|
|
+ interrupt-names = "vpss0";
|
|
+ };
|
|
+
|
|
+ vo: vo@11280000 {
|
|
+ compatible = "goke,vo";
|
|
+ reg = <0x11280000 0x40000>;
|
|
+ reg-names = "vo";
|
|
+ interrupts = <0 40 4>;
|
|
+ interrupt-names = "vo";
|
|
+ };
|
|
+
|
|
+ gfbg: gfbg@11280000 {
|
|
+ compatible = "goke,gfbg";
|
|
+ reg = <0x11280000 0x40000>;
|
|
+ reg-names = "gfbg";
|
|
+ interrupts = <0 41 4>;
|
|
+ interrupt-names = "gfbg";
|
|
+ };
|
|
+
|
|
+ vgs: vgs@11300000 {
|
|
+ compatible = "goke,vgs";
|
|
+ reg = <0x11300000 0x10000>;
|
|
+ reg-names = "vgs0";
|
|
+ interrupts = <0 49 4>;
|
|
+ interrupt-names = "vgs0";
|
|
+ };
|
|
+
|
|
+ gzip: gzip@11310000 {
|
|
+ compatible = "goke,gzip";
|
|
+ reg = <0x11310000 0x10000>;
|
|
+ reg-names = "gzip";
|
|
+ interrupts = <0 50 4>;
|
|
+ interrupt-names = "gzip";
|
|
+ };
|
|
+
|
|
+ vedu: vedu@11410000 {
|
|
+ compatible = "goke,vedu";
|
|
+ reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
|
|
+ reg-names = "vedu0", "jpge";
|
|
+ interrupts = <0 47 4>, <0 48 4>;
|
|
+ interrupt-names = "vedu0","jpge";
|
|
+ };
|
|
+
|
|
+ venc: venc {
|
|
+ compatible = "goke,venc";
|
|
+ };
|
|
+
|
|
+ aiao: aiao@100e0000 {
|
|
+ compatible = "goke,aiao";
|
|
+ reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
|
|
+ reg-names = "aiao","acodec";
|
|
+ interrupts = <0 42 4>;
|
|
+ interrupt-names = "AIO";
|
|
+ };
|
|
+
|
|
+ ive: ive@11320000 {
|
|
+ compatible = "goke,ive";
|
|
+ reg = <0x11320000 0x10000>;
|
|
+ reg-names = "ive";
|
|
+ interrupts = <0 51 4>;
|
|
+ interrupt-names = "ive";
|
|
+ };
|
|
+ };
|
|
+};
|