mirror of https://github.com/OpenIPC/firmware.git
				
				
				
			
		
			
				
	
	
		
			38 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			Diff
		
	
	
			
		
		
	
	
			38 lines
		
	
	
		
			1.4 KiB
		
	
	
	
		
			Diff
		
	
	
| --- linux-4.9.37/drivers/mtd/spi-nor/Kconfig	2017-07-12 16:42:41.000000000 +0300
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| +++ linux-4.9.y/drivers/mtd/spi-nor/Kconfig	2021-06-07 13:01:33.000000000 +0300
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| @@ -65,6 +65,34 @@
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|  	help
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|  	  This enables support for hisilicon SPI-NOR flash controller.
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|  
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| +config SPI_GOKE_SFC
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| +	tristate "Goke FMCV100 SPI-NOR Flash Controller(SFC)"
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| +	depends on ARCH_GOKE || ARCH_GOKE || COMPILE_TEST
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| +	depends on HAS_IOMEM && HAS_DMA
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| +	help
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| +	  This enables support for goke flash memory contrller ver100
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| +	  (FMCV100)- SPI-NOR flash controller.
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| +
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| +config CLOSE_SPI_8PIN_4IO
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| +	bool "Close SPI device Quad SPI mode for some 8PIN chip"
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| +	default y if ARCH_GOKE
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| +	help
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| +	fmcv100 and sfcv350 support Quad SPI mode and Quad&addr SPI mode.
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| +	But some 8PIN chip does not support this mode when HOLD/IO3 PIN
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| +	was used by reset operation.
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| +	Usually, your should not config this option.
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| +
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| +config GOKE_SPI_BLOCK_PROTECT
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| +	bool "Goke Spi Nor Device BP(Block Protect) Support"
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| +	depends on SPI_GOKE_SFC
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| +	default y if SPI_GOKE_SFC
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| +	help
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| +	  GOKE SFC supports BP(Block Protect) feature to preestablish a series
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| +	  area to avoid writing and erasing, except to reading. With this macro
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| +	  definition we can get the BP info which was setted before. The
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| +	  BOTTOM/TOP bit is setted to BOTTOM, it means the lock area starts
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| +	  from 0 address.
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| +
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|  config SPI_NXP_SPIFI
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|  	tristate "NXP SPI Flash Interface (SPIFI)"
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|  	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
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