mirror of https://github.com/OpenIPC/firmware.git
285 lines
9.1 KiB
Diff
285 lines
9.1 KiB
Diff
--- linux-4.9.37/drivers/mmc/host/sdhci.h 2017-07-12 16:42:41.000000000 +0300
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+++ linux-4.9.y/drivers/mmc/host/sdhci.h 2021-06-07 13:01:33.000000000 +0300
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@@ -20,6 +20,8 @@
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#include <linux/mmc/host.h>
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+#define SDHCI_GOKE_EDGE_TUNING /* enable edge tuning */
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+
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/*
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* Controller registers
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*/
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@@ -84,6 +86,7 @@
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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+#define SDHCI_CTRL_ADMA3 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_CTRL_CDTEST_INS 0x40
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#define SDHCI_CTRL_CDTEST_EN 0x80
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@@ -108,6 +111,7 @@
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#define SDHCI_DIV_MASK_LEN 8
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#define SDHCI_DIV_HI_MASK 0x300
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#define SDHCI_PROG_CLOCK_MODE 0x0020
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+#define SDHCI_CLOCK_PLL_EN 0x0008
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#define SDHCI_CLOCK_CARD_EN 0x0004
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#define SDHCI_CLOCK_INT_STABLE 0x0002
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#define SDHCI_CLOCK_INT_EN 0x0001
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@@ -132,6 +136,7 @@
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#define SDHCI_INT_CARD_REMOVE 0x00000080
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#define SDHCI_INT_CARD_INT 0x00000100
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#define SDHCI_INT_RETUNE 0x00001000
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+#define SDHCI_INT_CQE 0x00004000
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#define SDHCI_INT_ERROR 0x00008000
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#define SDHCI_INT_TIMEOUT 0x00010000
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#define SDHCI_INT_CRC 0x00020000
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@@ -141,14 +146,16 @@
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#define SDHCI_INT_DATA_CRC 0x00200000
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#define SDHCI_INT_DATA_END_BIT 0x00400000
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#define SDHCI_INT_BUS_POWER 0x00800000
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-#define SDHCI_INT_ACMD12ERR 0x01000000
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+#define SDHCI_INT_ACMD_ERR 0x01000000
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#define SDHCI_INT_ADMA_ERROR 0x02000000
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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- SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
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+ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \
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+ SDHCI_INT_ACMD_ERR)
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+
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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@@ -156,7 +163,13 @@
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SDHCI_INT_BLK_GAP)
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#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
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-#define SDHCI_ACMD12_ERR 0x3C
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+#define SDHCI_AUTO_CMD_ERR 0x3C
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+#define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001
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+#define SDHCI_AUTO_CMD_TIMEOUT_ERR 0x0002
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+#define SDHCI_AUTO_CMD_CRC_ERR 0x0004
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+#define SDHCI_AUTO_CMD_ENDBIT_ERR 0x0008
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+#define SDHCI_AUTO_CMD_INDEX_ERR 0x0010
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+#define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080
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#define SDHCI_HOST_CONTROL2 0x3E
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#define SDHCI_CTRL_UHS_MASK 0x0007
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@@ -165,7 +178,7 @@
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#define SDHCI_CTRL_UHS_SDR50 0x0002
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#define SDHCI_CTRL_UHS_SDR104 0x0003
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#define SDHCI_CTRL_UHS_DDR50 0x0004
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-#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
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+#define SDHCI_CTRL_HS400 0x0007 /* Non-standard */
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#define SDHCI_CTRL_VDD_180 0x0008
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#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
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#define SDHCI_CTRL_DRV_TYPE_B 0x0000
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@@ -174,6 +187,9 @@
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#define SDHCI_CTRL_DRV_TYPE_D 0x0030
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#define SDHCI_CTRL_EXEC_TUNING 0x0040
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#define SDHCI_CTRL_TUNED_CLK 0x0080
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+#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000
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+#define SDHCI_CTRL_ADDRESSING_64BIT 0x2000
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+#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000
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#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
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#define SDHCI_CAPABILITIES 0x40
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@@ -195,6 +211,7 @@
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#define SDHCI_CAN_VDD_300 0x02000000
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#define SDHCI_CAN_VDD_180 0x04000000
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#define SDHCI_CAN_64BIT 0x10000000
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+#define SDHCI_CAN_ASYNC_INT 0x20000000
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#define SDHCI_SUPPORT_SDR50 0x00000001
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#define SDHCI_SUPPORT_SDR104 0x00000002
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@@ -209,6 +226,7 @@
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#define SDHCI_RETUNING_MODE_SHIFT 14
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#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
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#define SDHCI_CLOCK_MUL_SHIFT 16
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+#define SDHCI_CAN_DO_ADMA3 0x08000000
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#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
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#define SDHCI_CAPABILITIES_1 0x44
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@@ -250,6 +268,9 @@
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#define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF
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#define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0
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+#define SDHCI_ADMA3_ID_ADDR_LOW 0x78
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+#define SDHCI_ADMA3_ID_ADDR_HI 0x7C
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+
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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@@ -260,7 +281,38 @@
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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-
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+#define SDHCI_SPEC_400 3
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+#define SDHCI_SPEC_410 4
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+#define SDHCI_SPEC_420 5
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+
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+#define SDHCI_MSHC_CTRL 0x508
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+#define SDHCI_CMD_CONFLIT_CHECK 0x01
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+
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+#define SDHCI_AXI_MBIIU_CTRL 0x510
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+#define SDHCI_GM_WR_OSRC_LMT_MASK (0x7 << 24)
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+#define SDHCI_GM_WR_OSRC_LMT_SEL(x) ((x) << 24)
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+#define SDHCI_GM_RD_OSRC_LMT_MASK (0x7 << 16)
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+#define SDHCI_GM_RD_OSRC_LMT_SEL(x) ((x) << 16)
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+#define SDHCI_UNDEFL_INCR_EN 0x1
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+
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+#define SDHCI_EMMC_CTRL 0x52c
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+#define SDHCI_CARD_IS_EMMC 0x00000001
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+#define SDHCI_ENH_STROBE_EN 0x00000100
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+
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+#define SDHCI_EMMC_HW_RESET 0x534
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+
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+#define SDHCI_AT_CTRL 0x540
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+#define SDHCI_SAMPLE_EN 0x00000010
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+
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+#define SDHCI_AT_STAT 0x544
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+#define SDHCI_PHASE_SEL_MASK 0x000000ff
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+
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+#define SDHCI_MULTI_CYCLE 0x54c
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+#define SDHCI_FOUND_EDGE (0x1 << 11)
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+#define SDHCI_EDGE_DETECT_EN (0x1 << 8)
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+#define SDHCI_DOUT_EN_F_EDGE (0x1 << 6)
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+#define SDHCI_DATA_DLY_EN (0x1 << 3)
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+#define SDHCI_CMD_DLY_EN (0x1 << 2)
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/*
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* End of controller registers.
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*/
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@@ -273,6 +325,7 @@
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*/
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#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
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#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
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+#define SDHCI_DMA_BOUNDARY_SIZE (0x1 << 27)
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/* ADMA2 32-bit DMA descriptor size */
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#define SDHCI_ADMA2_32_DESC_SZ 8
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@@ -298,6 +351,12 @@
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/* ADMA2 64-bit DMA descriptor size */
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#define SDHCI_ADMA2_64_DESC_SZ 12
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+/* ADMA3 32-bit DMA descriptor size */
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+#define SDHCI_ADMA3_32_DESC_SZ 8
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+
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+/* ADMA3 64-bit DMA descriptor size */
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+#define SDHCI_ADMA3_64_DESC_SZ 16
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+
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/*
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* ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
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* aligned.
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@@ -312,6 +371,9 @@
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#define ADMA2_TRAN_VALID 0x21
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#define ADMA2_NOP_END_VALID 0x3
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#define ADMA2_END 0x2
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+#define ADMA2_LINK_VALID 0x31
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+#define ADMA3_CMD_VALID 0x9
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+#define ADMA3_END 0x3b
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/*
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* Maximum segments assuming a 512KiB maximum requisition size and a minimum
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@@ -328,6 +390,18 @@
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COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
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};
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+struct card_info {
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+ unsigned int card_type;
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+ unsigned char timing;
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+ unsigned char card_connect;
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+#define CARD_CONNECT 1
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+#define CARD_DISCONNECT 0
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+ unsigned int card_support_clock; /* clock rate */
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+ unsigned int card_state; /* (our) card state */
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+ unsigned int sd_bus_speed;
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+ unsigned int ssr[16];
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+};
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+
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struct sdhci_host {
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/* Data set by hardware interface driver */
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const char *hw_name; /* Hardware bus name */
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@@ -425,6 +499,7 @@
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#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
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/* Broken Clock divider zero in controller */
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#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
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+#define SDHCI_QUIRK2_BROKEN_ADMA3 (1<<16)
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int irq; /* Device IRQ */
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void __iomem *ioaddr; /* Mapped address */
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@@ -458,6 +533,8 @@
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#define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */
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#define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */
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#define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */
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+#define SDHCI_USE_ADMA3 (1<<17) /* Host is ADMA3 capable */
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+#define SDHCI_HOST_VER4_ENABLE (1<<18) /* Host version 4 enable */
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unsigned int version; /* SDHCI spec. version */
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@@ -486,14 +563,21 @@
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void *adma_table; /* ADMA descriptor table */
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void *align_buffer; /* Bounce buffer */
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+ void *adma3_table; /* ADMA3 integrated descriptor table */
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+ void *cmd_table; /* ADMA3 command descriptor table */
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size_t adma_table_sz; /* ADMA descriptor table size */
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size_t align_buffer_sz; /* Bounce buffer size */
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+ size_t adma3_table_sz; /* ADMA3 integrated descriptor table size */
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+ size_t cmd_table_sz; /* ADMA3 command descriptor table size */
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dma_addr_t adma_addr; /* Mapped ADMA descr. table */
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dma_addr_t align_addr; /* Mapped bounce buffer */
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+ dma_addr_t adma3_addr; /* Mapped ADMA3 integrated descr. table */
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+ dma_addr_t cmd_addr; /* Mapped ADMA3 command descr. table */
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unsigned int desc_sz; /* ADMA descriptor size */
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+ unsigned int adma3_desc_sz; /* ADMA3 integrated descriptor size */
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struct tasklet_struct finish_tasklet; /* Tasklet structures */
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@@ -525,6 +609,10 @@
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#define SDHCI_TUNING_MODE_2 1
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#define SDHCI_TUNING_MODE_3 2
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+ struct cmdq_host *cq_host;
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+ unsigned int is_tuning;
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+ unsigned int error_count;
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+ struct card_info c_info;
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unsigned long private[0] ____cacheline_aligned;
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};
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@@ -564,6 +652,10 @@
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struct mmc_card *card,
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unsigned int max_dtr, int host_drv,
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int card_drv, int *drv_type);
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+ int (*start_signal_voltage_switch)(struct sdhci_host *host,
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+ struct mmc_ios *ios);
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+ void (*pre_init)(struct sdhci_host *host);
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+ void (*extra_init)(struct sdhci_host *host);
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};
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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@@ -698,4 +790,18 @@
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extern int sdhci_runtime_resume_host(struct sdhci_host *host);
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#endif
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+#define UNSTUFF_BITS(resp,start,size) \
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+ ({ \
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+ const int __size = size; \
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+ const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
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+ const int __off = 3 - ((start) / 32); \
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+ const int __shft = (start) & 31; \
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+ u32 __res; \
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+ \
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+ __res = resp[__off] >> __shft; \
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+ if (__size + __shft > 32) \
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+ __res |= resp[__off-1] << ((32 - __shft) % 32); \
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+ __res & __mask; \
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+ })
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+
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#endif /* __SDHCI_HW_H */
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