mirror of https://github.com/OpenIPC/firmware.git
237 lines
7.4 KiB
Diff
237 lines
7.4 KiB
Diff
--- linux-4.9.37/drivers/clk/goke/clk-gk7205v300.c 1970-01-01 03:00:00.000000000 +0300
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+++ linux-4.9.y/drivers/clk/goke/clk-gk7205v300.c 2021-06-07 13:01:33.000000000 +0300
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@@ -0,0 +1,233 @@
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+/*
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+ * Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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+ */
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+
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+#include <dt-bindings/clock/gk7205v300-clock.h>
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+#include <linux/clk-provider.h>
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+#include <linux/module.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include "clk.h"
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+#include "reset.h"
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+
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+static struct gk_fixed_rate_clock gk7205v300_fixed_rate_clks[] __initdata = {
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+ { GK7205V300_FIXED_100K, "100k", NULL, 0, 100000, },
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+ { GK7205V300_FIXED_400K, "400k", NULL, 0, 400000, },
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+ { GK7205V300_FIXED_3M, "3m", NULL, 0, 3000000, },
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+ { GK7205V300_FIXED_6M, "6m", NULL, 0, 6000000, },
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+ { GK7205V300_FIXED_12M, "12m", NULL, 0, 12000000, },
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+ { GK7205V300_FIXED_24M, "24m", NULL, 0, 24000000, },
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+ { GK7205V300_FIXED_25M, "25m", NULL, 0, 25000000, },
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+ { GK7205V300_FIXED_50M, "50m", NULL, 0, 50000000, },
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+ { GK7205V300_FIXED_83P3M, "83.3m",NULL, 0, 83300000, },
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+ { GK7205V300_FIXED_90M, "90m", NULL, 0, 90000000, },
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+ { GK7205V300_FIXED_100M, "100m", NULL, 0, 100000000, },
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+ { GK7205V300_FIXED_112M, "112m", NULL, 0, 112000000, },
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+ { GK7205V300_FIXED_125M, "125m", NULL, 0, 125000000, },
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+ { GK7205V300_FIXED_150M, "150m", NULL, 0, 150000000, },
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+ { GK7205V300_FIXED_200M, "200m", NULL, 0, 200000000, },
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+ { GK7205V300_FIXED_250M, "250m", NULL, 0, 250000000, },
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+ { GK7205V300_FIXED_300M, "300m", NULL, 0, 300000000, },
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+ { GK7205V300_FIXED_324M, "324m", NULL, 0, 324000000, },
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+ { GK7205V300_FIXED_342M, "342m", NULL, 0, 342000000, },
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+ { GK7205V300_FIXED_342M, "375m", NULL, 0, 375000000, },
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+ { GK7205V300_FIXED_400M, "400m", NULL, 0, 400000000, },
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+ { GK7205V300_FIXED_448M, "448m", NULL, 0, 448000000, },
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+ { GK7205V300_FIXED_500M, "500m", NULL, 0, 500000000, },
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+ { GK7205V300_FIXED_540M, "540m", NULL, 0, 540000000, },
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+ { GK7205V300_FIXED_600M, "600m", NULL, 0, 600000000, },
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+ { GK7205V300_FIXED_750M, "750m", NULL, 0, 750000000, },
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+ { GK7205V300_FIXED_1000M, "1000m",NULL, 0, 1000000000, },
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+ { GK7205V300_FIXED_1500M, "1500m",NULL, 0, 1500000000UL, },
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+};
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+
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+static const char *sysaxi_mux_p[] __initconst = {
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+ "24m", "200m"
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+};
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+static const char *sysapb_mux_p[] __initconst = {"24m", "50m"};
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+static const char *uart_mux_p[] __initconst = {"24m", "6m"};
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+static const char *fmc_mux_p[] __initconst = {"24m", "100m", "150m", "200m", "300m", "360m"};
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+static const char *mmc_mux_p[] __initdata = {
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+ "100k", "400k", "25m", "50m", "90m", "112m", "150m"
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+};
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+static const char *eth_mux_p[] __initconst = {"100m", "54m"};
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+static const char *usb_mux_p[] __initdata = {"phy", "crg",};
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+
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+static u32 sysaxi_mux_table[] = {0, 1};
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+static u32 sysapb_mux_table[] = {0, 1};
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+static u32 uart_mux_table[] = {0, 1};
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+static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
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+static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
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+static u32 eth_mux_table[] = {0, 1};
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+static u32 usb_mux_table[] = {0, 1};
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+
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+static struct gk_mux_clock gk7205v300_mux_clks[] __initdata = {
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+ {
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+ GK7205V300_SYSAXI_CLK, "sysaxi_mux", sysaxi_mux_p,
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+ ARRAY_SIZE(sysaxi_mux_p),
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+ CLK_SET_RATE_PARENT, 0x80, 6, 1, 0, sysaxi_mux_table,
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+ },
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+ {
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+ GK7205V300_SYSAPB_CLK, "sysapb_mux", sysapb_mux_p,
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+ ARRAY_SIZE(sysapb_mux_p),
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+ CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
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+ },
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+ {
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+ GK7205V300_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
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+ CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
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+ },
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+ {
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+ GK7205V300_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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+ CLK_SET_RATE_PARENT, 0x1f4, 24, 3, 0, mmc_mux_table,
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+ },
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+ {
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+ GK7205V300_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
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+ CLK_SET_RATE_PARENT, 0x22c, 24, 3, 0, mmc_mux_table,
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+ },
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+ {
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+ GK7205V300_UART_MUX, "uart_mux0", uart_mux_p,
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+ ARRAY_SIZE(uart_mux_p),
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+ CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
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+ },
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+ {
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+ GK7205V300_UART_MUX, "uart_mux1", uart_mux_p,
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+ ARRAY_SIZE(uart_mux_p),
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+ CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
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+ },
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+ {
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+ GK7205V300_UART_MUX, "uart_mux2", uart_mux_p,
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+ ARRAY_SIZE(uart_mux_p),
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+ CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
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+ },
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+ {
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+ GK7205V300_ETH_MUX, "eth_mux", eth_mux_p, ARRAY_SIZE(eth_mux_p),
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+ CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
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+ },
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+ {
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+ GK7205V300_USB2_MUX, "usb2_mux", usb_mux_p, ARRAY_SIZE(usb_mux_p),
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+ CLK_SET_RATE_PARENT, 0x140, 13, 0, 0, usb_mux_table
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+ },
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+};
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+
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+static struct gk_fixed_factor_clock gk7205v300_fixed_factor_clks[] __initdata = {
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+ {
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+ GK7205V300_SYSAXI_CLK, "clk_sysaxi", "sysaxi_mux", 1, 4,
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+ CLK_SET_RATE_PARENT
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+ },
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+};
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+
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+static struct gk_gate_clock gk7205v300_gate_clks[] __initdata = {
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+ /* fmc */
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+ {
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+ GK7205V300_FMC_CLK, "clk_fmc", "fmc_mux",
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+ CLK_SET_RATE_PARENT, 0x144, 1, 0,
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+ },
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+ /* mmc */
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+ {
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+ GK7205V300_MMC0_CLK, "clk_mmc0", "mmc0_mux",
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+ CLK_SET_RATE_PARENT, 0x1f4, 28, 0,
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+ },
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+ {
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+ GK7205V300_MMC1_CLK, "clk_mmc1", "mmc1_mux",
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+ CLK_SET_RATE_PARENT, 0x22c, 28, 0,
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+ },
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+ /* uart */
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+ {
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+ GK7205V300_UART0_CLK, "clk_uart0", "24m",
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+ CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
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+ },
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+ {
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+ GK7205V300_UART1_CLK, "clk_uart1", "24m",
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+ CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
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+ },
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+ {
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+ GK7205V300_UART2_CLK, "clk_uart2", "24m",
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+ CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
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+ },
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+ /* spi */
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+ {
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+ GK7205V300_SPI0_CLK, "clk_spi0", "100m",
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+ CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
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+ },
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+ {
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+ GK7205V300_SPI1_CLK, "clk_spi1", "100m",
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+ CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
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+ },
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+ /* i2c */
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+ {
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+ GK7205V300_I2C0_CLK, "clk_i2c0", "50m",
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+ CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
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+ },
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+ {
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+ GK7205V300_I2C1_CLK, "clk_i2c1", "50m",
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+ CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
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+ },
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+ {
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+ GK7205V300_I2C2_CLK, "clk_i2c2", "50m",
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+ CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
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+ },
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+ /* ethernet mac */
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+ {
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+ GK7205V300_ETH0_CLK, "clk_eth0", "eth_mux",
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+ CLK_SET_RATE_PARENT, 0x16c, 1, 0,
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+ },
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+ /* edmac */
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+ {
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+ GK7205V300_EDMAC_AXICLK, "axi_clk_edmac", NULL,
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+ CLK_SET_RATE_PARENT, 0x194, 2, 0,
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+ },
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+ {
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+ GK7205V300_EDMAC_CLK, "clk_edmac", NULL,
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+ CLK_SET_RATE_PARENT, 0x194, 1, 0,
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+ },
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+ /* usb */
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+ {
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+ GK7205V300_USB2_BUS_CLK, "clk_usb2_bus", "usb2_mux",
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+ CLK_SET_RATE_PARENT, 0x140, 8, 0,
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+ },
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+ {
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+ GK7205V300_USB2_REF_CLK, "clk_usb2_ref", "usb2_mux",
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+ CLK_SET_RATE_PARENT, 0x140, 9, 0,
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+ },
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+ {
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+ GK7205V300_USB2_UTMI_CLK, "clk_usb2_utmi", "usb2_mux",
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+ CLK_SET_RATE_PARENT, 0x140, 12, 0,
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+ },
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+ {
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+ GK7205V300_USB2_PHY_APB_CLK, "clk_u2phy_apb_ref",NULL,
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+ CLK_SET_RATE_PARENT, 0x140, 11, 0,
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+ },
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+ {
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+ GK7205V300_USB2_PHY_PLL_CLK, "clk_u2phy_pll_ref",NULL,
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+ CLK_SET_RATE_PARENT, 0x140, 4, 0,
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+ },
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+ {
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+ GK7205V300_USB2_PHY_XO_CLK, "clk_u2phy_xo_ref",NULL,
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+ CLK_SET_RATE_PARENT, 0x140, 2, 0,
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+ },
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+};
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+
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+static void __init gk7205v300_clk_init(struct device_node *np)
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+{
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+ struct gk_clock_data *clk_data;
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+
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+ clk_data = gk_clk_init(np, GK7205V300_NR_CLKS);
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+ if (!clk_data)
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+ return;
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+ if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
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+ gk_reset_init(np, GK7205V300_NR_RSTS);
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+
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+ gk_clk_register_fixed_rate(gk7205v300_fixed_rate_clks,
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+ ARRAY_SIZE(gk7205v300_fixed_rate_clks),
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+ clk_data);
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+ gk_clk_register_mux(gk7205v300_mux_clks, ARRAY_SIZE(gk7205v300_mux_clks),
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+ clk_data);
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+ gk_clk_register_fixed_factor(gk7205v300_fixed_factor_clks,
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+ ARRAY_SIZE(gk7205v300_fixed_factor_clks), clk_data);
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+ gk_clk_register_gate(gk7205v300_gate_clks,
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+ ARRAY_SIZE(gk7205v300_gate_clks), clk_data);
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+
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+}
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+
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+CLK_OF_DECLARE(gk7205v300_clk, "goke,gk7205v300-clock", gk7205v300_clk_init);
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+
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