mirror of https://github.com/OpenIPC/firmware.git
25 lines
879 B
Diff
25 lines
879 B
Diff
--- linux-4.9.37/arch/arm/boot/compressed/head.S 2017-07-12 16:42:41.000000000 +0300
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+++ linux-4.9.y/arch/arm/boot/compressed/head.S 2021-06-07 13:01:32.000000000 +0300
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@@ -218,6 +218,21 @@
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addcc r0, r0, pc
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cmpcc r4, r0
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orrcc r4, r4, #1 @ remember we skipped cache_on
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+
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+/*TODO all the Cortex-A7 Single Core must fix this bug */
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+#if defined(CONFIG_ARCH_GK7205V200) || defined(CONFIG_ARCH_GK7205V300) \
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+ || defined(CONFIG_ARCH_GK7202V300) || defined(CONFIG_ARCH_GK7605V100)
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+/*
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+ * This is a bug on Cortex-A7 MPCORE. see buglist of Cortex-A7
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+ * The D-caches are disabled when ACTLR.SMP is set to 0 regardless of the
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+ * value of the cache enable bit. so we must set SMP bit of ACTLR register
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+ * before enable D cache
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+ */
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+ mrc p15, 0, r0, c1, c0, 1
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+ orr r0, #(1 << 6)
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+ mcr p15, 0, r0, c1, c0, 1
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+#endif
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+
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blcs cache_on
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restart: adr r0, LC0
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