mirror of https://github.com/OpenIPC/firmware.git
29 lines
1.5 KiB
Diff
29 lines
1.5 KiB
Diff
diff -drupN a/include/linux/clk-provider.h b/include/linux/clk-provider.h
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--- a/include/linux/clk-provider.h 2018-08-06 17:23:04.000000000 +0300
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+++ b/include/linux/clk-provider.h 2022-06-12 05:28:14.000000000 +0300
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@@ -25,7 +25,7 @@
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#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
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#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
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#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
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- /* unused */
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+#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
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#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
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#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
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#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
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@@ -35,6 +35,15 @@
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#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
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/* parents need enable during gate/ungate, set rate and re-parent */
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#define CLK_OPS_PARENT_ENABLE BIT(12)
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+#define CLK_IGNORE_AUTORESET BIT(13) /* for sunxi use */
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+#define CLK_REVERT_ENABLE BIT(14) /* for sunxi use */
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+#define CLK_IGNORE_SYNCBOOT BIT(15) /* for sunxi use */
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+#define CLK_READONLY BIT(16) /* for sunxi use */
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+#define CLK_IGNORE_DISABLE BIT(17) /* for sunxi use */
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+#define CLK_RATE_FLAT_FACTORS BIT(18) /* for sunxi use */
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+#define CLK_RATE_FLAT_DELAY BIT(19) /* for sunxi use */
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+#define CLK_NO_DISABLE BIT(20) /* for sunxi use */
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+#define CLK_IGNORE_ENABLE_DISABLE BIT(21) /* for sunxi use */
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struct clk;
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struct clk_hw;
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