mirror of https://github.com/OpenIPC/firmware.git
141 lines
4.3 KiB
Diff
141 lines
4.3 KiB
Diff
diff -drupN a/drivers/w1/masters/sunxi-owc.h b/drivers/w1/masters/sunxi-owc.h
|
|
--- a/drivers/w1/masters/sunxi-owc.h 1970-01-01 03:00:00.000000000 +0300
|
|
+++ b/drivers/w1/masters/sunxi-owc.h 2022-06-12 05:28:14.000000000 +0300
|
|
@@ -0,0 +1,136 @@
|
|
+/*
|
|
+ * drivers/char/sunxi-owc/sunxi-owc.h
|
|
+ *
|
|
+ * Copyright (C) 2019 Allwinner.
|
|
+ * lihuaxing <lihuaxing@allwinnertech.com>
|
|
+ *
|
|
+ * SUNXI OWC Register Definition
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of
|
|
+ * the License, or (at your option) any later version.
|
|
+ */
|
|
+
|
|
+#ifndef __SUNXI_OWC_H__
|
|
+#define __SUNXI_OWC_H__
|
|
+
|
|
+//#include "smartcard.h"
|
|
+//#include "sunxi-scr-user.h"
|
|
+
|
|
+#define OWC_MODULE_NAME "sunxi_owc_char_class"
|
|
+
|
|
+#define OWC_IOCTL_BASE 'O'
|
|
+#define BIT_WRITE _IOW(OWC_IOCTL_BASE, 0, u8)
|
|
+#define BIT_READ _IOR(OWC_IOCTL_BASE, 1, u8)
|
|
+#define BYTE_WRITE _IOW(OWC_IOCTL_BASE, 2, u8)
|
|
+#define BYTE_READ _IOR(OWC_IOCTL_BASE, 3, u8)
|
|
+#define HDQ_WRITE _IOW(OWC_IOCTL_BASE, 4, u8)
|
|
+#define HDQ_READ _IOR(OWC_IOCTL_BASE, 5, u8)
|
|
+
|
|
+/* owc registers */
|
|
+#define OW_DATA (0x000)
|
|
+#define OW_CTL (0x004)
|
|
+#define OW_SMSC (0x008)
|
|
+#define OW_SMCRC (0x00c)
|
|
+#define OW_INT_STATUS (0x010)
|
|
+#define OW_INT_CTL (0x014)
|
|
+#define OW_FCLK (0x018)
|
|
+#define OW_LC (0x01c)
|
|
+#define SM_WR_RD_TCTL (0x020)
|
|
+#define SM_RST_PRESENCE_TCTL (0x024)
|
|
+#define SP_WR_RD_TCTL (0x028)
|
|
+#define SP_BR_TCTL (0x02c)
|
|
+
|
|
+/* owc intterrupt config register */
|
|
+#define OWC_INT_MASK 0X3F
|
|
+#define INTEN_DGCH (0x1<<5)
|
|
+#define INTEN_ST_CRC_FINI (0X1<<4)
|
|
+#define INTEN_WR_CPL (0X1<<3)
|
|
+#define INTEN_RD_CPL (0X1<<2)
|
|
+#define INTEN_SP_TIME_OUT (0x1<<1)
|
|
+#define INTEN_ST_INIT_SP_CPL (0X1<<0)
|
|
+
|
|
+/* owc interrupt status */
|
|
+#define INT_DGCH_OCCUR (0x1<<5)
|
|
+#define INT_ST_CRC_FINI (0x1<<4)
|
|
+#define INT_OW_WR_CPL (0x1<<3)
|
|
+#define INT_OW_RD_CPL (0x1<<2)
|
|
+#define INT_SP_TIME_OUT (0x1<<1)
|
|
+#define INT_ST_INIT_SP_CPL (0x1<<0)
|
|
+
|
|
+/* owc standard timing config */
|
|
+#define TSU 0x01
|
|
+#define TREC 0x01
|
|
+#define TRDV 0x0E
|
|
+#define TLOW0 0x45
|
|
+#define TLOW1 0x01
|
|
+#define TSLOT 0x78
|
|
+#define TPDL 0x46
|
|
+#define TPDH 0x05 /* slave presence first sample:<=0x1b for DS2431 */
|
|
+#define TRSTL 0x1E9
|
|
+#define TRSTH 0x1E9
|
|
+#define TIMEOUT 1000
|
|
+
|
|
+/* owc HDQ timing config */
|
|
+#define RD_SAMPLE_POINT 0
|
|
+#define THW1_INT 0x20
|
|
+#define THW1_DEC 0
|
|
+#define THW0 0x87
|
|
+#define TCYCH 0xBE
|
|
+#define TB 0xBE
|
|
+#define TBR 0x28
|
|
+
|
|
+#define OW_FCLK_MASK (0x1F<<16)
|
|
+#define OW_FCLK_D_MASK (0xFF)
|
|
+
|
|
+#define SCR_BUF_SIZE 256
|
|
+#define SCR_FIFO_DEPTH 8 /* just half of hw fifo size */
|
|
+#define SCR_RX_TRANSMIT_NOYET 0
|
|
+#define SCR_RX_TRANSMIT_TMOUT 1 /* time out */
|
|
+
|
|
+/* ROM command */
|
|
+#define SEARCH 0xF0
|
|
+#define READ_ROM 0x33
|
|
+#define MATCH_ROM 0x55
|
|
+#define JUMP_ROM 0xCC
|
|
+#define WARN_ROM 0xEC
|
|
+
|
|
+
|
|
+
|
|
+enum scr_atr_status {
|
|
+ SCR_ATR_RESP_INVALID,
|
|
+ SCR_ATR_RESP_FAIL,
|
|
+ SCR_ATR_RESP_OK,
|
|
+};
|
|
+
|
|
+
|
|
+
|
|
+struct sunxi_owc {
|
|
+ void __iomem *reg_base;
|
|
+ struct clk *mclk;
|
|
+ struct clk *pclk;
|
|
+ struct platform_device *pdev;
|
|
+ struct pinctrl *pctrl;
|
|
+ struct resource *mem_res;
|
|
+ struct class *owc_dev_class;
|
|
+ struct device *owc_device;
|
|
+ uint32_t clk_freq;
|
|
+ uint32_t func_clk;
|
|
+ uint32_t irq_num;
|
|
+ struct cdev cdev;
|
|
+ dev_t chrdev;
|
|
+ spinlock_t owc_lock;
|
|
+ bool presence_status;
|
|
+ bool init_status;
|
|
+ wait_queue_head_t r_wait;
|
|
+ wait_queue_head_t w_wait;
|
|
+ wait_queue_head_t crc_wait;
|
|
+ bool write_flg;
|
|
+ bool single_bit;
|
|
+ u8 rom_data[10];
|
|
+ u8 w_data[10];
|
|
+ struct completion done;
|
|
+};
|
|
+
|
|
+#endif
|