mirror of https://github.com/OpenIPC/firmware.git
101 lines
3.5 KiB
Diff
101 lines
3.5 KiB
Diff
diff -drupN a/drivers/rtc/rtc-sunxi-v2.h b/drivers/rtc/rtc-sunxi-v2.h
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--- a/drivers/rtc/rtc-sunxi-v2.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/rtc/rtc-sunxi-v2.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,96 @@
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+/*
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+ * Some macro and struct of SUNXI RTC-V2.
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+ *
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+ * Copyright (C) 2018 Allwinner.
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+ *
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+ * Damon <liush@allwinnertech.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#ifndef _RTC_SUNXI_V2_H_
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+#define _RTC_SUNXI_V2_H_
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+
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+#include "rtc-sunxi-common.h"
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+
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+#define SUNXI_RTC_BGR_REG 0x20c
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+#define SUNXI_RTC_GATING_ENABLE BIT(31)
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+
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+#define SUNXI_DCXO_CFG 0x40
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+#define SUNXI_CLK_REQ_ENABLE BIT(31)
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+#define SUNXI_DXCO_ENBALE BIT(0)
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+
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+#define SUNXI_SPI_CLK_CFG_REG 0x50
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+#define SUNXI_RTC_SPI_CLK_ENABLE BIT(31)
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+#define SUNXI_RTC_SPI_CLK_DIV 0
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+
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+#define SUNXI_RTC_SPI_CFG_REG 0x54
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+#define SUNXI_RTC_SPI_OP_BUSY 31
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+#define SUNXI_RTC_SPI_CFG_BUSY 30
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+#define SUNXI_RTC_REG_ACCESS_WAY 24
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+#define SUNXI_RTC_REG_ACCESS_ADDR 16
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+#define SUNXI_RTC_REG_ACCESS_WRITE_VAL 8
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+#define SUNXI_RTC_REG_ACCESS_READ_VAL 0
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+
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+#define SUNXI_LOSC_CTRL 0x0
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+#define SUNXI_RC16M_OUT_ENABLE BIT(7)
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+#define SUNXI_LOSC_AUTO_SWT_ENABLE BIT(6)
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+#define SUNXI_LOSC_AUTO_SWT_PEND_ENABLE BIT(5)
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+#define SUNXI_EXT_LOSC_ENABLE BIT(4)
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+#define SUNXI_EXT_LOSC_GSM 2
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+#define SUNXI_RTC_CLK_SRC 0
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+
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+#define SUNXI_LOSC_AUTO_ST_STA 0x1
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+#define SUNXI_EXT_LOSC_STA 2
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+#define SUNXI_LOSC_AUTO_SWT_PEND 1
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+#define SUNXI_LOSC_SRC_SEL_STA 0
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+
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+#define SUNXI_INTOSC_CLK_PRESCAL 0X2
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+#define SUNXI_INTOSC_32KCLK_PRESCAL 0
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+
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+#define SUNXI_RTC_DH_CFG 0X3
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+#define SUNXI_RTC_HIGH_DAY 0
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+
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+#define SUNXI_RTC_DL_CFG 0X4
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+#define SUNXI_RTC_LOW_DAY 0
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+
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+#define SUNXI_RTC_HH_CFG 0X5
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+#define SUNXI_RTC_HOUR 0
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+
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+#define SUNXI_RTC_MM_CFG 0X6
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+#define SUNXI_RTC_MIN 0
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+
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+#define SUNXI_RTC_SS_CFG 0X7
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+#define SUNXI_RTC_SEC 0
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+
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+#define SUNXI_RTC_TIMER_READ_CFG 0X8
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+#define SUNXI_RTC_TIMER_READ_LOCK_BYPASS BIT(2)
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+#define SUNXI_RTC_TIMER_READ_LOCK_ENABLE BIT(1)
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+#define SUNXI_RTC_TIMER_VAL_CFG_ENABLE BIT(0)
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+
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+#define SUNXI_RTC_DH_RD 0X9
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+#define SUNXI_RTC_DL_RD 0Xa
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+#define SUNXI_RTC_HH_RD 0Xb
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+#define SUNXI_RTC_MM_RD 0Xc
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+#define SUNXI_RTC_SS_RD 0Xd
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+#define SUNXI_ALMCFG_DH 0Xe
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+#define SUNXI_ALMCFG_DL 0Xf
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+#define SUNXI_ALMCFG_HH 0X10
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+#define SUNXI_ALMCFG_MM 0X11
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+#define SUNXI_ALMCFG_SS 0X12
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+
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+#define SUNXI_ALM0_ENABLE_REG 0X13
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+#define SUNXI_ALM0_WAKEUP 2
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+#define SUNXI_ALM0_IRQ_ENABLE BIT(1)
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+#define SUNXI_ALM0_ENABLE BIT(0)
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+
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+#define SUNXI_ALM0_IRQ_STA 0x14
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+#define SUNXI_ALM0_IRQ_PEND 0
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+
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+#define SUNXI_LOSC_OUT_GATE 0X15
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+#define SUNXI_LOSC_OUT_SEL 1
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+#define SUNXI_LOSC_OUT_GATING 0
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+
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+#endif /* end of _RTC_SUNXI_V2_H_ */
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