mirror of https://github.com/OpenIPC/firmware.git
773 lines
24 KiB
Diff
773 lines
24 KiB
Diff
diff -drupN a/drivers/mmc/host/sunxi-mmc-v5p3x.c b/drivers/mmc/host/sunxi-mmc-v5p3x.c
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--- a/drivers/mmc/host/sunxi-mmc-v5p3x.c 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/mmc/host/sunxi-mmc-v5p3x.c 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,768 @@
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+/*
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+* Sunxi SD/MMC host driver
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+*
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+* Copyright (C) 2015 AllWinnertech Ltd.
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+* Author: lixiang <lixiang@allwinnertech>
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+*
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+* This program is free software; you can redistribute it and/or modify
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+* it under the terms of the GNU General Public License version 2 as
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+* published by the Free Software Foundation.
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+*
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+* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+* kind, whether express or implied; without even the implied warranty
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+* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+* GNU General Public License for more details.
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+*/
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+
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+
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+#include <linux/clk.h>
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+#include <linux/clk/sunxi.h>
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+
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+#include <linux/gpio.h>
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+#include <linux/platform_device.h>
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+#include <linux/spinlock.h>
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+#include <linux/scatterlist.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/slab.h>
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+#include <linux/reset.h>
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+
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+#include <linux/of_address.h>
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+#include <linux/of_gpio.h>
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+#include <linux/of_platform.h>
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+
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+#include <linux/mmc/host.h>
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+#include <linux/mmc/sd.h>
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+#include <linux/mmc/sdio.h>
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+#include <linux/mmc/mmc.h>
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+#include <linux/mmc/core.h>
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+#include <linux/mmc/card.h>
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+#include <linux/mmc/slot-gpio.h>
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+
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+#include "sunxi-mmc.h"
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+#include "sunxi-mmc-v5p3x.h"
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+#include "sunxi-mmc-export.h"
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+
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+#define SUNXI_RETRY_CNT_PER_PHA_V5P3X 3
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+
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+/*dma triger level setting*/
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+#define SUNXI_DMA_TL_SDMMC_V5P3X ((0x2<<28)|(7<<16)|248)
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+/*one dma des can transfer data size = 1<<SUNXI_DES_SIZE_SDMMC*/
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+
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+#define SUNXI_DES_SIZE_SDMMC_V5P3X (12)
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+
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+/*reg*/
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+/*SMHC eMMC4.5 DDR Start Bit Detection Control Register */
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+/*SMHC CRC Status Detect Control Register */
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+/*SMHC Card Threshold Control Register */
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+/*SMHC Drive Delay Control Register */
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+/*SMHC Sample Delay Control Register */
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+/*SMHC Data Strobe Delay Control Register */
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+/*SMHC NewTiming Set Register */
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+#define SDXC_REG_EDSD (0x010C)
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+#define SDXC_REG_CSDC (0x0054)
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+#define SDXC_REG_THLD (0x0100)
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+#define SDXC_REG_DRV_DL (0x0140)
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+#define SDXC_REG_SAMP_DL (0x0144)
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+#define SDXC_REG_DS_DL (0x0148)
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+#define SDXC_REG_SD_NTSR (0x005C)
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+#define SDXC_REG_SMCV (0x300) /*SMHC Version Register */
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+
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+/*bit*/
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+#define SDXC_HS400_MD_EN (1U<<31)
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+#define SDXC_CARD_WR_THLD_ENB (1U<<2)
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+#define SDXC_CARD_RD_THLD_ENB (1U)
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+
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+#define SDXC_DAT_DRV_PH_SEL (1U<<17)
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+#define SDXC_CMD_DRV_PH_SEL (1U<<16)
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+#define SDXC_SAMP_DL_SW_EN (1u<<7)
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+#define SDXC_DS_DL_SW_EN (1u<<7)
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+
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+#define SDXC_2X_TIMING_MODE (1U<<31)
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+#define SDXC_HS400_NEW_SAMPLE_EN (1U<<0)
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+
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+/*mask*/
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+#define SDXC_CRC_DET_PARA_MASK (0xf)
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+#define SDXC_CARD_RD_THLD_MASK (0x0FFF0000)
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+#define SDXC_TX_TL_MASK (0xff)
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+#define SDXC_RX_TL_MASK (0x00FF0000)
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+
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+#define SDXC_SAMP_DL_SW_MASK (0x0000003F)
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+#define SDXC_DS_DL_SW_MASK (0x0000003F)
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+
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+#define SDXC_STIMING_CMD_PH_MASK (0x00000030)
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+#define SDXC_STIMING_DAT_PH_MASK (0x00000300)
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+
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+/*value*/
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+#define SDXC_CRC_DET_PARA_HS400 (6)
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+#define SDXC_CRC_DET_PARA_OTHER (3)
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+#define SDXC_FIFO_DETH (1024>>2)
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+
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+/*size*/
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+#define SDXC_CARD_RD_THLD_SIZE (0x00000FFF)
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+
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+/*shit*/
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+#define SDXC_CARD_RD_THLD_SIZE_SHIFT (16)
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+
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+#define SDXC_STIMING_CMD_PH_SHIFT (4)
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+#define SDXC_STIMING_DAT_PH_SHIFT (8)
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+
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+/*Sunxi MMC Host Controller Version*/
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+#define SMHC_VERSION_V5P3 0x50300
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+
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+
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+enum sunxi_mmc_clk_mode {
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+ mmc_clk_400k = 0,
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+ mmc_clk_26M,
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+ mmc_clk_52M,
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+ mmc_clk_52M_DDR4,
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+ mmc_clk_52M_DDR8,
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+ mmc_clk_104M,
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+ mmc_clk_208M,
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+ mmc_clk_104M_DDR,
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+ mmc_clk_208M_DDR,
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+ mmc_clk_mod_num,
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+};
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+
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+struct sunxi_mmc_clk_dly {
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+ enum sunxi_mmc_clk_mode cmod;
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+ char *mod_str;
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+ u32 cmd_drv_ph;
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+ u32 dat_drv_ph;
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+ u32 sam_dly;
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+ u32 ds_dly;
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+ u32 sam_ph_dat;
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+ u32 sam_ph_cmd;
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+};
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+
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+struct sunxi_mmc_spec_regs {
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+ u32 drv_dl; /*REG_DRV_DL */
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+ u32 samp_dl; /*REG_SAMP_DL */
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+ u32 ds_dl; /*REG_DS_DL */
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+ u32 sd_ntsr; /*REG_SD_NTSR */
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+};
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+
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+struct sunxi_mmc_ver_priv {
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+ struct sunxi_mmc_spec_regs bak_spec_regs;
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+ struct sunxi_mmc_clk_dly mmc_clk_dly[mmc_clk_mod_num];
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+};
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+
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+
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+static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *host, int clk,
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+ int bus_width, int timing)
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+{
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+ struct mmc_host *mhost = host->mmc;
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+ u32 rval = 0;
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+ enum sunxi_mmc_clk_mode cmod = mmc_clk_400k;
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+ u32 in_clk_dly[6] = { 0 };
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+ int ret = 0;
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+ struct device_node *np = NULL;
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+ struct sunxi_mmc_clk_dly *mmc_clk_dly =
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+ ((struct sunxi_mmc_ver_priv *)host->version_priv_dat)->mmc_clk_dly;
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+
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+ if (!mhost->parent || !mhost->parent->of_node) {
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+ dev_err(mmc_dev(host->mmc),
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+ "no dts to parse clk dly,use default\n");
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+ return;
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+ }
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+
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+ np = mhost->parent->of_node;
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+
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+ if (clk <= 400 * 1000) {
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+ cmod = mmc_clk_400k;
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+ } else if (clk <= 26 * 1000 * 1000) {
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+ cmod = mmc_clk_26M;
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+ } else if (clk <= 52 * 1000 * 1000) {
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+ if ((bus_width == MMC_BUS_WIDTH_4)
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+ && sunxi_mmc_ddr_timing(timing)) {
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+ cmod = mmc_clk_52M_DDR4;
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+ } else if ((bus_width == MMC_BUS_WIDTH_8)
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+ && (timing == MMC_TIMING_MMC_DDR52)) {
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+ cmod = mmc_clk_52M_DDR8;
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+ } else {
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+ cmod = mmc_clk_52M;
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+ }
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+ } else if (clk <= 104 * 1000 * 1000) {
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+ if ((bus_width == MMC_BUS_WIDTH_8)
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+ && (timing == MMC_TIMING_MMC_HS400)) {
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+ cmod = mmc_clk_104M_DDR;
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+ } else {
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+ cmod = mmc_clk_104M;
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+ }
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+ } else if (clk <= 208 * 1000 * 1000) {
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+ if ((bus_width == MMC_BUS_WIDTH_8)
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+ && (timing == MMC_TIMING_MMC_HS400)) {
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+ cmod = mmc_clk_208M_DDR;
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+ } else {
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+ cmod = mmc_clk_208M;
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+ }
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+ } else {
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+ dev_err(mmc_dev(mhost), "clk %d is out of range\n", clk);
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+ return;
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+ }
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+
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+ ret = of_property_read_u32_array(np, mmc_clk_dly[cmod].mod_str,
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+ in_clk_dly, ARRAY_SIZE(in_clk_dly));
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+ if (ret) {
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+ dev_dbg(mmc_dev(host->mmc), "failed to get %s used default\n",
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+ mmc_clk_dly[cmod].mod_str);
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+ } else {
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+ mmc_clk_dly[cmod].cmd_drv_ph = in_clk_dly[0];
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+ mmc_clk_dly[cmod].dat_drv_ph = in_clk_dly[1];
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+ /*mmc_clk_dly[cmod].sam_dly = in_clk_dly[2]; */
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+ /*mmc_clk_dly[cmod].ds_dly = in_clk_dly[3]; */
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+ mmc_clk_dly[cmod].sam_ph_dat = in_clk_dly[4];
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+ mmc_clk_dly[cmod].sam_ph_cmd = in_clk_dly[5];
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+ dev_dbg(mmc_dev(host->mmc), "Get %s clk dly ok\n",
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+ mmc_clk_dly[cmod].mod_str);
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+
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+ }
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+
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+ dev_dbg(mmc_dev(host->mmc), "Try set %s clk dly ok\n",
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+ mmc_clk_dly[cmod].mod_str);
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+ dev_dbg(mmc_dev(host->mmc), "cmd_drv_ph %d\n",
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+ mmc_clk_dly[cmod].cmd_drv_ph);
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+ dev_dbg(mmc_dev(host->mmc), "dat_drv_ph %d\n",
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+ mmc_clk_dly[cmod].dat_drv_ph);
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+ dev_dbg(mmc_dev(host->mmc), "sam_ph_dat %d\n",
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+ mmc_clk_dly[cmod].sam_ph_dat);
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+ dev_dbg(mmc_dev(host->mmc), "sam_ph_cmd %d\n",
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+ mmc_clk_dly[cmod].sam_ph_cmd);
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+
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+ rval = mmc_readl(host, REG_DRV_DL);
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+ if (mmc_clk_dly[cmod].cmd_drv_ph)
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+ rval |= SDXC_CMD_DRV_PH_SEL; /*180 phase */
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+ else
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+ rval &= ~SDXC_CMD_DRV_PH_SEL; /*90 phase */
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+
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+ if (mmc_clk_dly[cmod].dat_drv_ph)
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+ rval |= SDXC_DAT_DRV_PH_SEL; /*180 phase */
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+ else
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+ rval &= ~SDXC_DAT_DRV_PH_SEL; /*90 phase */
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+
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+ mmc_writel(host, REG_DRV_DL, rval);
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+
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+/*
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+* rval = mmc_readl(host,REG_SAMP_DL);
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+* rval &= ~SDXC_SAMP_DL_SW_MASK;
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+* rval |= mmc_clk_dly[cmod].sam_dly & SDXC_SAMP_DL_SW_MASK;
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+* rval |= SDXC_SAMP_DL_SW_EN;
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+* mmc_writel(host,REG_SAMP_DL,rval);
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+*
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+* rval = mmc_readl(host,REG_DS_DL);
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+* rval &= ~SDXC_DS_DL_SW_MASK;
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+* rval |= mmc_clk_dly[cmod].ds_dly & SDXC_DS_DL_SW_MASK;
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+* rval |= SDXC_DS_DL_SW_EN;
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+* mmc_writel(host,REG_DS_DL,rval);
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+*/
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+
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+ rval = mmc_readl(host, REG_SD_NTSR);
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+ rval &= ~SDXC_STIMING_DAT_PH_MASK;
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+ rval |=
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+ (mmc_clk_dly[cmod].
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+ sam_ph_dat << SDXC_STIMING_DAT_PH_SHIFT) &
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+ SDXC_STIMING_DAT_PH_MASK;
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+ mmc_writel(host, REG_SD_NTSR, rval);
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+
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+ rval = mmc_readl(host, REG_SD_NTSR);
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+ rval &= ~SDXC_STIMING_CMD_PH_MASK;
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+ rval |=
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+ (mmc_clk_dly[cmod].
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+ sam_ph_cmd << SDXC_STIMING_CMD_PH_SHIFT) &
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+ SDXC_STIMING_CMD_PH_MASK;
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+ mmc_writel(host, REG_SD_NTSR, rval);
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+
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+ dev_dbg(mmc_dev(host->mmc), " REG_DRV_DL %08x\n",
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+ mmc_readl(host, REG_DRV_DL));
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+ dev_dbg(mmc_dev(host->mmc), " REG_SAMP_DL %08x\n",
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+ mmc_readl(host, REG_SAMP_DL));
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+ dev_dbg(mmc_dev(host->mmc), " REG_DS_DL %08x\n",
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+ mmc_readl(host, REG_DS_DL));
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+ dev_dbg(mmc_dev(host->mmc), " REG_SD_NTSR %08x\n",
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+ mmc_readl(host, REG_SD_NTSR));
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+
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+}
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+
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+static int __sunxi_mmc_do_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en,
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+ u32 pwr_save, u32 ignore_dat0)
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+{
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+ unsigned long expire = jiffies + msecs_to_jiffies(250);
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+ u32 rval;
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+
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+ rval = mmc_readl(host, REG_CLKCR);
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+ rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
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+
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+ if (oclk_en)
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+ rval |= SDXC_CARD_CLOCK_ON;
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+ if (pwr_save)
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+ rval |= SDXC_LOW_POWER_ON;
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+ if (ignore_dat0)
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+ rval |= SDXC_MASK_DATA0;
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+
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+ mmc_writel(host, REG_CLKCR, rval);
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+
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+ dev_dbg(mmc_dev(host->mmc), "%s REG_CLKCR:%x\n", __func__,
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+ mmc_readl(host, REG_CLKCR));
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+
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+ rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
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+ mmc_writel(host, REG_CMDR, rval);
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+
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+ do {
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+ rval = mmc_readl(host, REG_CMDR);
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+ } while (time_before(jiffies, expire) && (rval & SDXC_START));
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+
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+ /* clear irq status bits set by the command */
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+ mmc_writel(host, REG_RINTR,
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+ mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
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+
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+ if (rval & SDXC_START) {
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+ dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
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+ return -EIO;
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+ }
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+
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+ /*only use mask data0 when update clk,clear it when not update clk */
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+ if (ignore_dat0)
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+ mmc_writel(host, REG_CLKCR,
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+ mmc_readl(host, REG_CLKCR) & ~SDXC_MASK_DATA0);
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+
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+ return 0;
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+}
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+
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+static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
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+{
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+ struct device_node *np = NULL;
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+ struct mmc_host *mmc = host->mmc;
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+ int pwr_save = 0;
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+ int len = 0;
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+
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+ if (!mmc->parent || !mmc->parent->of_node) {
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+ dev_err(mmc_dev(host->mmc),
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+ "no dts to parse power save mode\n");
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+ return -EIO;
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+ }
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+
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+ np = mmc->parent->of_node;
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+ if (of_find_property(np, "sunxi-power-save-mode", &len))
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+ pwr_save = 1;
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+ return __sunxi_mmc_do_oclk_onoff(host, oclk_en, pwr_save, 1);
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+}
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+
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+static void sunxi_mmc_2xmod_onoff(struct sunxi_mmc_host *host, u32 newmode_en)
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+{
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+ u32 rval = mmc_readl(host, REG_SD_NTSR);
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+
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+ if (newmode_en)
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+ rval |= SDXC_2X_TIMING_MODE;
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+ else
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+ rval &= ~SDXC_2X_TIMING_MODE;
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+
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+ mmc_writel(host, REG_SD_NTSR, rval);
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+
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+ dev_dbg(mmc_dev(host->mmc), "REG_SD_NTSR: 0x%08x ,val %x\n",
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+ mmc_readl(host, REG_SD_NTSR), rval);
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+}
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+
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+static int sunxi_mmc_clk_set_rate_for_sdmmc_v5p3x(struct sunxi_mmc_host *host,
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+ struct mmc_ios *ios)
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+{
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+ u32 mod_clk = 0;
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+ u32 src_clk = 0;
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+ u32 rval = 0;
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+ s32 err = 0;
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+ u32 rate = 0;
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+ char *sclk_name = NULL;
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+ struct clk *mclk = host->clk_mmc;
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+ struct clk *sclk = NULL;
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+ struct device *dev = mmc_dev(host->mmc);
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+ int div = 0;
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+#ifdef MMC_FPGA
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+ void __iomem *ctl_2x_en = ioremap(0x03000024, 0x4);
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+#endif
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+ if (ios->clock == 0) {
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+ __sunxi_mmc_do_oclk_onoff(host, 0, 0, 1);
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+ return 0;
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+ }
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+ if (sunxi_mmc_ddr_timing(ios->timing)) {
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+ mod_clk = ios->clock << 2;
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+ div = 1;
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+ } else {
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+ mod_clk = ios->clock << 1;
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+ div = 0;
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+ }
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+ sclk = clk_get(dev, "osc24m");
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+ sclk_name = "osc24m";
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+ if (IS_ERR(sclk)) {
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+ dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n",
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+ sclk_name);
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+ return -1;
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+ }
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+
|
|
+ src_clk = clk_get_rate(sclk);
|
|
+ if (mod_clk > src_clk) {
|
|
+ clk_put(sclk);
|
|
+ sclk = clk_get(dev, "pll_periph");
|
|
+ sclk_name = "pll_periph";
|
|
+ }
|
|
+ if (IS_ERR(sclk)) {
|
|
+ dev_err(mmc_dev(host->mmc), "Error to get source clock %s\n",
|
|
+ sclk_name);
|
|
+ return -1;
|
|
+ }
|
|
+
|
|
+ sunxi_mmc_oclk_onoff(host, 0);
|
|
+
|
|
+ err = clk_set_parent(mclk, sclk);
|
|
+ if (err) {
|
|
+ dev_err(mmc_dev(host->mmc), "set parent failed\n");
|
|
+ clk_put(sclk);
|
|
+ return -1;
|
|
+ }
|
|
+
|
|
+ rate = clk_round_rate(mclk, mod_clk);
|
|
+
|
|
+ dev_dbg(mmc_dev(host->mmc), "get round rate %d\n", rate);
|
|
+
|
|
+ /*clk_disable_unprepare(host->clk_mmc);*/
|
|
+
|
|
+ err = clk_set_rate(mclk, rate);
|
|
+ if (err) {
|
|
+ dev_err(mmc_dev(host->mmc), "set mclk rate error, rate %dHz\n",
|
|
+ rate);
|
|
+ clk_put(sclk);
|
|
+ return -1;
|
|
+ }
|
|
+/*
|
|
+ rval = clk_prepare_enable(host->clk_mmc);
|
|
+ if (rval) {
|
|
+ dev_err(mmc_dev(host->mmc), "Enable mmc clk err %d\n", rval);
|
|
+ return -1;
|
|
+ }
|
|
+*/
|
|
+ src_clk = clk_get_rate(sclk);
|
|
+ clk_put(sclk);
|
|
+
|
|
+ dev_dbg(mmc_dev(host->mmc), "set round clock %d, soure clk is %d\n",
|
|
+ rate, src_clk);
|
|
+
|
|
+#ifdef MMC_FPGA
|
|
+ if (sunxi_mmc_ddr_timing(ios->timing)) {
|
|
+ /* clear internal divider */
|
|
+ rval = mmc_readl(host, REG_CLKCR);
|
|
+ rval &= ~0xff;
|
|
+ rval |= 1;
|
|
+ }
|
|
+ mmc_writel(host, REG_CLKCR, rval);
|
|
+
|
|
+ rval = mmc_readl(host, REG_DRV_DL);
|
|
+ if (ios->clock > 400 * 1000) {
|
|
+ rval |= (1 << 7);
|
|
+ mmc_writel(host, REG_DRV_DL, rval);
|
|
+ } else {
|
|
+ if (sunxi_mmc_ddr_timing(ios->timing))
|
|
+ dev_info(mmc_dev(host->mmc), "Warning: is 400KHz DDR mode");
|
|
+ rval &= ~(1 << 7);
|
|
+ mmc_writel(host, REG_DRV_DL, rval);
|
|
+ }
|
|
+ dev_info(mmc_dev(host->mmc), "FPGA REG_CLKCR: 0x%08x\n",
|
|
+ mmc_readl(host, REG_CLKCR));
|
|
+#else
|
|
+ /* clear internal divider */
|
|
+ rval = mmc_readl(host, REG_CLKCR);
|
|
+ rval &= ~0xff;
|
|
+ rval |= div;
|
|
+ mmc_writel(host, REG_CLKCR, rval);
|
|
+#endif
|
|
+#ifdef MMC_FPGA
|
|
+ /* Because V7 FPGA board only support 1xmode, use 0x03000024 Bit3 to control 1xmode or 2xmode ,*/
|
|
+ rval = readl(ctl_2x_en);
|
|
+ /*sunxi_of_parse_clk_dly(host); */
|
|
+ if (rval & (0x1 << 3))
|
|
+ sunxi_mmc_2xmod_onoff(host, 1);
|
|
+ else
|
|
+ sunxi_mmc_2xmod_onoff(host, 0);
|
|
+
|
|
+ iounmap(ctl_2x_en);
|
|
+#else
|
|
+ sunxi_mmc_2xmod_onoff(host, 1);
|
|
+#endif
|
|
+ if ((ios->bus_width == MMC_BUS_WIDTH_8)
|
|
+ && (ios->timing == MMC_TIMING_MMC_HS400)
|
|
+ ) {
|
|
+ rval = mmc_readl(host, REG_EDSD);
|
|
+ rval |= SDXC_HS400_MD_EN;
|
|
+ mmc_writel(host, REG_EDSD, rval);
|
|
+ rval = mmc_readl(host, REG_CSDC);
|
|
+ rval &= ~SDXC_CRC_DET_PARA_MASK;
|
|
+ rval |= SDXC_CRC_DET_PARA_HS400;
|
|
+ mmc_writel(host, REG_CSDC, rval);
|
|
+
|
|
+ rval = mmc_readl(host, REG_SD_NTSR);
|
|
+ rval |= SDXC_HS400_NEW_SAMPLE_EN;
|
|
+ mmc_writel(host, REG_SD_NTSR, rval);
|
|
+ } else {
|
|
+ rval = mmc_readl(host, REG_EDSD);
|
|
+ rval &= ~SDXC_HS400_MD_EN;
|
|
+ mmc_writel(host, REG_EDSD, rval);
|
|
+ rval = mmc_readl(host, REG_CSDC);
|
|
+ rval &= ~SDXC_CRC_DET_PARA_MASK;
|
|
+ rval |= SDXC_CRC_DET_PARA_OTHER;
|
|
+ mmc_writel(host, REG_CSDC, rval);
|
|
+ }
|
|
+ dev_dbg(mmc_dev(host->mmc), "SDXC_REG_EDSD: 0x%08x\n",
|
|
+ mmc_readl(host, REG_EDSD));
|
|
+ dev_dbg(mmc_dev(host->mmc), "SDXC_REG_CSDC: 0x%08x\n",
|
|
+ mmc_readl(host, REG_CSDC));
|
|
+
|
|
+ if (sunxi_mmc_ddr_timing(ios->timing))
|
|
+ ios->clock = rate >> 2;
|
|
+ else
|
|
+ ios->clock = rate >> 1;
|
|
+
|
|
+ sunxi_mmc_set_clk_dly(host, ios->clock, ios->bus_width, ios->timing);
|
|
+
|
|
+ return sunxi_mmc_oclk_onoff(host, 1);
|
|
+}
|
|
+
|
|
+static void sunxi_mmc_thld_ctl_for_sdmmc_v5p3x(struct sunxi_mmc_host *host,
|
|
+ struct mmc_ios *ios,
|
|
+ struct mmc_data *data)
|
|
+{
|
|
+ u32 bsz = data->blksz;
|
|
+ /*unit:byte */
|
|
+ /*u32 tdtl = (host->dma_tl & SDXC_TX_TL_MASK)<<2;*/
|
|
+ /*unit:byte */
|
|
+ u32 rdtl = ((host->dma_tl & SDXC_RX_TL_MASK) >> 16) << 2;
|
|
+ u32 rval = 0;
|
|
+
|
|
+ if ((data->flags & MMC_DATA_READ)
|
|
+ && (bsz <= SDXC_CARD_RD_THLD_SIZE)
|
|
+ /*((SDXC_FIFO_DETH<<2)-bsz) >= (rdtl) */
|
|
+ && ((SDXC_FIFO_DETH << 2) >= (rdtl + bsz))
|
|
+ && ((ios->timing == MMC_TIMING_MMC_HS200)
|
|
+ || (ios->timing == MMC_TIMING_UHS_SDR50)
|
|
+ || (ios->timing == MMC_TIMING_UHS_SDR104))) {
|
|
+ rval = mmc_readl(host, REG_THLD);
|
|
+ rval &= ~SDXC_CARD_RD_THLD_MASK;
|
|
+ rval |= data->blksz << SDXC_CARD_RD_THLD_SIZE_SHIFT;
|
|
+ rval |= SDXC_CARD_RD_THLD_ENB;
|
|
+ mmc_writel(host, REG_THLD, rval);
|
|
+ } else {
|
|
+ rval = mmc_readl(host, REG_THLD);
|
|
+ rval &= ~SDXC_CARD_RD_THLD_ENB;
|
|
+ mmc_writel(host, REG_THLD, rval);
|
|
+ }
|
|
+
|
|
+ dev_dbg(mmc_dev(host->mmc), "SDXC_REG_THLD: 0x%08x\n",
|
|
+ mmc_readl(host, REG_THLD));
|
|
+
|
|
+}
|
|
+
|
|
+static void sunxi_mmc_save_spec_reg_v5p3x(struct sunxi_mmc_host *host)
|
|
+{
|
|
+ struct sunxi_mmc_spec_regs *spec_regs =
|
|
+ &((struct sunxi_mmc_ver_priv *)(host->version_priv_dat))->
|
|
+ bak_spec_regs;
|
|
+ spec_regs->drv_dl = mmc_readl(host, REG_DRV_DL);
|
|
+ spec_regs->samp_dl = mmc_readl(host, REG_SAMP_DL);
|
|
+ spec_regs->ds_dl = mmc_readl(host, REG_DS_DL);
|
|
+ spec_regs->sd_ntsr = mmc_readl(host, REG_SD_NTSR);
|
|
+}
|
|
+
|
|
+static void sunxi_mmc_restore_spec_reg_v5p3x(struct sunxi_mmc_host *host)
|
|
+{
|
|
+ struct sunxi_mmc_spec_regs *spec_regs =
|
|
+ &((struct sunxi_mmc_ver_priv *)(host->version_priv_dat))->
|
|
+ bak_spec_regs;
|
|
+ mmc_writel(host, REG_DRV_DL, spec_regs->drv_dl);
|
|
+ mmc_writel(host, REG_SAMP_DL, spec_regs->samp_dl);
|
|
+ mmc_writel(host, REG_DS_DL, spec_regs->ds_dl);
|
|
+ mmc_writel(host, REG_SD_NTSR, spec_regs->sd_ntsr);
|
|
+}
|
|
+
|
|
+static inline void sunxi_mmc_set_dly_raw(struct sunxi_mmc_host *host,
|
|
+ s32 opha_cmd, s32 ipha_cmd,
|
|
+ s32 opha_dat, s32 ipha_dat)
|
|
+{
|
|
+ u32 rval = mmc_readl(host, REG_DRV_DL);
|
|
+
|
|
+ if (opha_cmd > 0)
|
|
+ rval |= SDXC_CMD_DRV_PH_SEL; /*180 phase */
|
|
+ else if (opha_cmd == 0)
|
|
+ rval &= ~SDXC_CMD_DRV_PH_SEL; /*90 phase */
|
|
+
|
|
+ if (opha_dat > 0)
|
|
+ rval |= SDXC_DAT_DRV_PH_SEL; /*180 phase */
|
|
+ else if (opha_dat == 0)
|
|
+ rval &= ~SDXC_DAT_DRV_PH_SEL; /*90 phase */
|
|
+
|
|
+ mmc_writel(host, REG_DRV_DL, rval);
|
|
+
|
|
+ rval = mmc_readl(host, REG_SD_NTSR);
|
|
+
|
|
+ if (ipha_cmd >= 0) {
|
|
+ rval &= ~SDXC_STIMING_CMD_PH_MASK;
|
|
+ rval |=
|
|
+ (ipha_cmd << SDXC_STIMING_CMD_PH_SHIFT) &
|
|
+ SDXC_STIMING_CMD_PH_MASK;
|
|
+ }
|
|
+
|
|
+ if (ipha_dat >= 0) {
|
|
+ rval &= ~SDXC_STIMING_DAT_PH_MASK;
|
|
+ rval |=
|
|
+ (ipha_dat << SDXC_STIMING_DAT_PH_SHIFT) &
|
|
+ SDXC_STIMING_DAT_PH_MASK;
|
|
+ }
|
|
+
|
|
+ rval &= ~SDXC_2X_TIMING_MODE;
|
|
+ mmc_writel(host, REG_SD_NTSR, rval);
|
|
+ rval |= SDXC_2X_TIMING_MODE;
|
|
+ mmc_writel(host, REG_SD_NTSR, rval);
|
|
+
|
|
+ dev_info(mmc_dev(host->mmc), "REG_DRV_DL: 0x%08x\n",
|
|
+ mmc_readl(host, REG_DRV_DL));
|
|
+ dev_info(mmc_dev(host->mmc), "REG_SD_NTSR: 0x%08x\n",
|
|
+ mmc_readl(host, REG_SD_NTSR));
|
|
+}
|
|
+
|
|
+static int sunxi_mmc_judge_retry_v5p3x(struct sunxi_mmc_host *host,
|
|
+ struct mmc_command *cmd, u32 rcnt,
|
|
+ u32 errno, void *other)
|
|
+{
|
|
+ /****-1 means use default value***/
|
|
+ /*
|
|
+ *We use {-1,-1} as first member,because we want to
|
|
+ *retry current delay first.
|
|
+ *Only If current delay failed,we try new delay
|
|
+ */
|
|
+ const s32 sunxi_phase[10][2] = { {-1, -1},
|
|
+ {1, 1}, {0, 0}, {1, 0}, {0, 1}, {1, 2}, {0, 2} };
|
|
+
|
|
+ if (rcnt < (SUNXI_RETRY_CNT_PER_PHA_V5P3X * 10)) {
|
|
+ sunxi_mmc_set_dly_raw(host,
|
|
+ sunxi_phase[rcnt /
|
|
+ SUNXI_RETRY_CNT_PER_PHA_V5P3X]
|
|
+ [0],
|
|
+ sunxi_phase[rcnt /
|
|
+ SUNXI_RETRY_CNT_PER_PHA_V5P3X]
|
|
+ [1],
|
|
+ sunxi_phase[rcnt /
|
|
+ SUNXI_RETRY_CNT_PER_PHA_V5P3X]
|
|
+ [0],
|
|
+ sunxi_phase[rcnt /
|
|
+ SUNXI_RETRY_CNT_PER_PHA_V5P3X]
|
|
+ [1]);
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ sunxi_mmc_set_dly_raw(host, sunxi_phase[0][0],
|
|
+ sunxi_phase[0][1],
|
|
+ sunxi_phase[0][0], sunxi_phase[0][1]);
|
|
+ dev_info(mmc_dev(host->mmc), "sunxi v5p3x retry give up\n");
|
|
+ return -1;
|
|
+}
|
|
+
|
|
+void sunxi_mmc_init_priv_v5p3x(struct sunxi_mmc_host *host,
|
|
+ struct platform_device *pdev, int phy_index)
|
|
+{
|
|
+ struct sunxi_mmc_ver_priv *ver_priv =
|
|
+ devm_kzalloc(&pdev->dev, sizeof(struct sunxi_mmc_ver_priv),
|
|
+ GFP_KERNEL);
|
|
+ host->version_priv_dat = ver_priv;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].cmod = mmc_clk_400k;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].mod_str = "sunxi-dly-400k";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].dat_drv_ph = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].sam_ph_dat = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_400k].sam_ph_cmd = 0;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].cmod = mmc_clk_26M;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].mod_str = "sunxi-dly-26M";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].dat_drv_ph = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].sam_ph_dat = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_26M].sam_ph_cmd = 0;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].cmod = mmc_clk_52M,
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].mod_str = "sunxi-dly-52M";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].dat_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].sam_ph_dat = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M].sam_ph_cmd = 1;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].cmod = mmc_clk_52M_DDR4;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].mod_str = "sunxi-dly-52M-ddr4";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].dat_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].sam_ph_dat = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR4].sam_ph_cmd = 1;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].cmod = mmc_clk_52M_DDR8;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].mod_str = "sunxi-dly-52M-ddr8";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].dat_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].sam_ph_dat = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_52M_DDR8].sam_ph_cmd = 1;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].cmod = mmc_clk_104M;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].mod_str = "sunxi-dly-104M";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].dat_drv_ph = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].sam_ph_dat = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M].sam_ph_cmd = 0;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].cmod = mmc_clk_208M;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].mod_str = "sunxi-dly-208M";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].dat_drv_ph = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].sam_ph_dat = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M].sam_ph_cmd = 0;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].cmod = mmc_clk_104M_DDR;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].mod_str = "sunxi-dly-104M-ddr";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].dat_drv_ph = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].sam_ph_dat = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_104M_DDR].sam_ph_cmd = 0;
|
|
+
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].cmod = mmc_clk_208M_DDR;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].mod_str = "sunxi-dly-208M-ddr";
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].cmd_drv_ph = 1;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].dat_drv_ph = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].sam_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].ds_dly = 0;
|
|
+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].sam_ph_dat = 0;
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+ ver_priv->mmc_clk_dly[mmc_clk_208M_DDR].sam_ph_cmd = 0;
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+
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+ host->sunxi_mmc_clk_set_rate = sunxi_mmc_clk_set_rate_for_sdmmc_v5p3x;
|
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+ host->dma_tl = SUNXI_DMA_TL_SDMMC_V5P3X;
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+ host->idma_des_size_bits = SUNXI_DES_SIZE_SDMMC_V5P3X;
|
|
+ host->sunxi_mmc_thld_ctl = sunxi_mmc_thld_ctl_for_sdmmc_v5p3x;
|
|
+ host->sunxi_mmc_save_spec_reg = sunxi_mmc_save_spec_reg_v5p3x;
|
|
+ host->sunxi_mmc_restore_spec_reg = sunxi_mmc_restore_spec_reg_v5p3x;
|
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+ sunxi_mmc_reg_ex_res_inter(host, phy_index);
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|
+ host->sunxi_mmc_set_acmda = sunxi_mmc_set_a12a;
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|
+ host->phy_index = phy_index;
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|
+ host->sunxi_mmc_oclk_en = sunxi_mmc_oclk_onoff;
|
|
+ host->sunxi_mmc_judge_retry = sunxi_mmc_judge_retry_v5p3x;
|
|
+ /*sunxi_of_parse_clk_dly(host); */
|
|
+ if (mmc_readl(host, REG_SMCV) == SMHC_VERSION_V5P3) {
|
|
+ host->des_addr_shift = 2;
|
|
+ }
|
|
+
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(sunxi_mmc_init_priv_v5p3x);
|