mirror of https://github.com/OpenIPC/firmware.git
118 lines
4.1 KiB
Diff
118 lines
4.1 KiB
Diff
diff -drupN a/drivers/leds/leds-is31fl3736.h b/drivers/leds/leds-is31fl3736.h
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--- a/drivers/leds/leds-is31fl3736.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/leds/leds-is31fl3736.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,113 @@
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+/*
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+ * drivers/leds/is31fl3736.h
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+ * Driver for ISSI is31fl3736 of I2C LED controllers
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+ *
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+ * Copyright (C) 2018 Allwinner Technology Limited. All rights reserved.
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+ *
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+#ifndef IS31FL3736_H_
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+#define IS31FL3736_H_
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+
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+#ifndef BIT
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+#define BIT(x) (1 << (x))
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+#endif
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+
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+/**< contorl regs */
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+/*!< Available page 0 to page 3 registers */
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+#define IS31FL3736_REG_CMD 0xfd
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+/*!< to lock/unlock command reg */
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+#define IS31FL3736_RET_CMD_LOCK 0xfe
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+ /*!< configure the interrupt func */
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+#define IS31FL3736_REG_INTR_MASK 0XF0
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+/*!< show the interrupt status */
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+#define IS31FL3736_REG_INTR_STATUS 0XF1
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+
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+//CS-X 1~8; SW-Y 1 ~ 12; all == 8 * 12 == 96
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+
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+/**< when REG_CMD is 0x00, control page 0 regs */
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+/*i: 0--24*/
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+/*!< Set on or off state for each LED R(0~17h) (W) */
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+#define IS31FL3736_REG_PG0_SWITCH(i) (0x00 + (i))
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+/*!< Store open state for each LED R(0~17h) (R) */
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+#define IS31FL3736_REG_PG0_OPEN_STATUS(i) (0x18 + (i))
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+ /*!< Store short state for each LED R(0~17h) (R) */
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+#define IS31FL3736_REG_PG0_SHORT_STATUS(i) (0x30 + (i))
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+
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+/**< when REG_CMD is 0x01, control page 1 regs */
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+/*!< Set PWM duty for LED R(0~BEh) (W) */
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+#define IS31FL3736_REG_PG1_PWM(i) (i)
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+
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+/**< when REG_CMD is 0x02, control page 2 regs */
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+/*!< Set operating mode of each dot R(0~BEh) (W) */
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+#define IS31FL3736_REG_PG2_BREATH(i) (i)
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+
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+/**< when REG_CMD is 0x03, control page 3 regs */
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+/*!< Configure the operation mode (W) */
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+#define IS31FL3736_REG_PG3_CONFIG 0X00
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+
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+/* is31fl3736_NORMAL_EN_M : W ;bitpos:[0] ;default: 1'b0 ; */
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+/*description: When SSD is "0"*/
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+/*IS31FL3736 works in software shutdown mode and to */
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+/*normal operate the SSD bit should set to "1".*/
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+#define IS31FL3736_NORMAL_EN_M (BIT(0))
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+#define IS31FL3736_NORMAL_EN_V (0x1)
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+#define IS31FL3736_NORMAL_EN_S (0)
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+
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+/* is31fl3736_BREATH_EN_M : W ;bitpos:[1] ;default: 1'b0 ; */
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+/*description: those dots select working in ABM-x mode will*/
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+/*start to run the pre-established timing. */
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+/*If it is disabled, all dots work in PWM mode. */
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+#define IS31FL3736_BREATH_EN_M (BIT(1))
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+#define IS31FL3736_BREATH_EN_V (0x1)
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+#define IS31FL3736_BREATH_EN_S (1)
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+
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+#define IS31FL3736_SYNC_EN_M ((IS31FL3736_SYNC_EN_V) << (IS31FL3736_SYNC_EN_S))
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+#define IS31FL3736_SYNC_EN_V (0x3)
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+#define IS31FL3736_SYNC_EN_S (6)
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+
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+/*!< Set the global current (W) */
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+#define IS31FL3736_REG_PG3_CURR 0X01
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+/*!< Set fade in and hold time for breath function of ABMi R(1~3) (W) */
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+#define IS31FL3736_REG_PG3_FADE_IN(i) (0x02 + (i - 1) * 4)
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+/*!< Set fade out and hold time for breath function of ABMi R(1~3) (W) */
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+#define IS31FL3736_REG_PG3_FADE_OUT(i) (0x03 + (i - 1) * 4)
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+
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+#define IS31FL3736_ABM_T1_V (0x7)
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+#define IS31FL3736_ABM_T1_S (5)
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+
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+#define IS31FL3736_ABM_T2_V (0x7)
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+#define IS31FL3736_ABM_T2_S (1)
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+
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+#define IS31FL3736_ABM_T3_V (0x7)
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+#define IS31FL3736_ABM_T3_S (5)
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+
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+#define IS31FL3736_ABM_T4_V (0x7)
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+#define IS31FL3736_ABM_T4_S (1)
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+
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+/*!< Set loop characters of ABM-i R(1~3) (W) */
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+#define IS31FL3736_REG_PG3_LOOP1(i) (0x04 + (i - 1) * 4)
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+/*!< Set loop characters of ABM-i R(1~3) (W) */
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+#define IS31FL3736_REG_PG3_LOOP2(i) (0x05 + (i - 1) * 4)
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+
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+#define IS31FL3736_ABM_LTA_V (0xf)
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+#define IS31FL3736_ABM_LTA_S (0)
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+
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+#define IS31FL3736_ABM_LTB_V (0xff)
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+#define IS31FL3736_ABM_LTB_S (0)
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+
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+/*!< Update the setting of 02h ~ 0Dh registers (W) */
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+#define IS31FL3736_REG_PG3_UPDATE 0X0E
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+/*!< Set the pull-up resistor for SWy (W) */
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+#define IS31FL3736_REG_PG3_SW_PULLUP 0X0F
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+ /*!< Set the pull-down resistor for CSx (W) */
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+#define IS31FL3736_REG_PG3_CS_PULLDOWN 0X10
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+ /*!< Reset all register to POR state (R) */
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+#define IS31FL3736_REG_PG3_RESET 0X11
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+
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+#endif
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+
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