mirror of https://github.com/OpenIPC/firmware.git
79 lines
2.8 KiB
Diff
79 lines
2.8 KiB
Diff
diff -drupN a/drivers/clk/sunxi/clk-sunxi.h b/drivers/clk/sunxi/clk-sunxi.h
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--- a/drivers/clk/sunxi/clk-sunxi.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/clk/sunxi/clk-sunxi.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,74 @@
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+/*
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+ * Copyright (C) 2013 Allwinnertech, kevin.z.m <kevin@allwinnertech.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * Adjustable factor-based clock implementation
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+ */
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+#ifndef __MACH_SUNXI_CLK_SUNXI_H
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+#define __MACH_SUNXI_CLK_SUNXI_H
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+
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+#define to_clk_factor(_hw) container_of(_hw, struct sunxi_clk_factors, hw)
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+
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+#define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift))
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+#define CLRMASK(width, shift) (~(SETMASK(width, shift)))
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+#define GET_BITS(shift, width, reg) \
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+ (((reg) & SETMASK(width, shift)) >> (shift))
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+#define SET_BITS(shift, width, reg, val) \
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+ (((reg) & CLRMASK(width, shift)) | (val << (shift)))
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+
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+#define __SUNXI_ALL_CLK_IGNORE_UNUSED__ 1
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+
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+struct sunxi_reg_ops {
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+ u32 (*reg_readl)(void __iomem *reg);
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+ void (*reg_writel)(u32 val, void __iomem *reg);
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+};
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+#ifdef CONFIG_PM_SLEEP
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+struct sunxi_factor_clk_reg_cache {
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+ struct list_head node;
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+ void __iomem *config_reg;
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+ u32 config_value;
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+ void __iomem *sdmpat_reg;
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+ u32 sdmpat_value;
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+};
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+struct sunxi_periph_clk_reg_cache {
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+ struct list_head node;
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+ void __iomem *mux_reg;
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+ u32 mux_value;
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+ void __iomem *divider_reg;
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+ u32 divider_value;
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+ void __iomem *gate_enable_reg;
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+ u32 gate_enable_value;
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+ void __iomem *gate_reset_reg;
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+ u32 gate_reset_value;
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+ void __iomem *gate_bus_reg;
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+ u32 gate_bus_value;
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+ void __iomem *gate_dram_reg;
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+ u32 gate_dram_value;
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+};
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+#endif
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+
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+#ifdef CONFIG_PM_SLEEP
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+extern struct list_head clk_periph_reg_cache_list;
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+extern struct list_head clk_factor_reg_cache_list;
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+void sunxi_factor_clk_save(struct sunxi_factor_clk_reg_cache *factor_clk_reg);
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+void sunxi_factor_clk_restore(struct sunxi_factor_clk_reg_cache *factor_clk_reg);
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+void sunxi_periph_clk_save(struct sunxi_periph_clk_reg_cache *periph_clk_reg);
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+void sunxi_periph_clk_restore(struct sunxi_periph_clk_reg_cache *periph_clk_reg);
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+#endif
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+
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+extern spinlock_t clk_lock;
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+extern void __iomem *sunxi_clk_base;
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+extern void __iomem *sunxi_clk_cpus_base;
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+extern void __iomem *sunxi_clk_rtc_base;
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+
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+void __init sunxi_clocks_init(struct device_node *node);
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+void __init sunxi_cpu_clocks_init(struct device_node *node);
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+
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+struct factor_init_data *sunxi_clk_get_factor_by_name(const char *name);
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+struct periph_init_data *sunxi_clk_get_periph_by_name(const char *name);
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+struct periph_init_data *sunxi_clk_get_periph_rtc_by_name(const char *name);
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+struct periph_init_data *sunxi_clk_get_periph_cpus_by_name(const char *name);
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+#endif
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