mirror of https://github.com/OpenIPC/firmware.git
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
diff -drupN a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
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--- a/arch/arm/mm/proc-v7.S 2018-08-06 17:23:04.000000000 +0300
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+++ b/arch/arm/mm/proc-v7.S 2022-06-12 05:28:14.000000000 +0300
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@@ -93,7 +93,7 @@ ENDPROC(cpu_v7_dcache_clean_area)
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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-.equ cpu_v7_suspend_size, 4 * 9
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+.equ cpu_v7_suspend_size, 4 * 11
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r11, lr}
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@@ -112,7 +112,13 @@ ENTRY(cpu_v7_do_suspend)
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mrc p15, 0, r8, c1, c0, 0 @ Control register
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mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
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- stmia r0, {r5 - r11}
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+ stmia r0!, {r5 - r11}
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+#ifdef CONFIG_ARM_LPAE
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+ mrrc p15, 1, r4, r5, c2 @ TTB 0
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+#else
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+ mrc p15, 0, r4, c2, c0, 0 @ TTB 0
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+#endif
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+ stmia r0, {r4 - r5}
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_v7_do_suspend)
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@@ -123,7 +129,7 @@ ENTRY(cpu_v7_do_resume)
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ldmia r0!, {r4 - r5}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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- ldmia r0, {r5 - r11}
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+ ldmia r0!, {r5 - r11}
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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@@ -133,14 +139,14 @@ ENTRY(cpu_v7_do_resume)
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#else
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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- mcr p15, 0, r1, c2, c0, 0 @ TTB 0
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+ mcr p15, 0, r1, c2, c0, 0 @ TTB 0, it is idmap_pgd to prepare enable mmu
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mcr p15, 0, r7, c2, c0, 1 @ TTB 1
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#endif
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mcr p15, 0, r11, c2, c0, 2 @ TTB control register
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ldr r4, =PRRR @ PRRR
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- ldr r5, =NMRR @ NMRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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- mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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+ ldr r4, =NMRR @ NMRR
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+ mcr p15, 0, r4, c10, c2, 1 @ write NMRR
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#endif /* CONFIG_MMU */
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mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
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teq r4, r9 @ Is it already set?
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@@ -148,6 +154,7 @@ ENTRY(cpu_v7_do_resume)
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mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
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isb
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dsb
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+ ldmia r0, {r1 - r2} @ TTBR0 for current
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mov r0, r8 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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