mirror of https://github.com/OpenIPC/firmware.git
67 lines
2.4 KiB
Diff
67 lines
2.4 KiB
Diff
diff -drupN a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
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--- a/arch/arm/mach-sunxi/sunxi.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/arch/arm/mach-sunxi/sunxi.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,62 @@
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+/*
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+ * Generic definitions for Allwinner SunXi SoCs
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+ *
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+ * Copyright (C) 2012 Maxime Ripard
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+ *
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+ * Maxime Ripard <maxime.ripard@free-electrons.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#ifndef __MACH_SUNXI_H
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+#define __MACH_SUNXI_H
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+
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+#if defined(CONFIG_ARCH_SUN8IW8P1)
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+#define SUNXI_SRAM_A1_PBASE (0x00000000)
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+#define SUNXI_SRAM_A1_SIZE (0x4000)
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+#define SUNXI_SRAM_C_PBASE (0x00004000)
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+#define SUNXI_SRAM_C_SIZE (0x00014000)
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+
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+#elif defined(CONFIG_ARCH_SUN8IW10P1)
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+#define SUNXI_SRAM_A1_PBASE (0x00000000)
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+#define SUNXI_SRAM_A1_SIZE (0x4000)
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+#define SUNXI_SRAM_C_PBASE (0x00004000)
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+#define SUNXI_SRAM_C_SIZE (0x9000)
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+
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+#elif defined(CONFIG_ARCH_SUN8IW11P1)
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+#define SUNXI_SRAM_A1_PBASE (0x00000000)
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+#define SUNXI_SRAM_A1_SIZE (0x4000)
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+#define SUNXI_SRAM_A_PBASE (0x00000000)
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+#define SUNXI_SRAM_A_SIZE (0xC000)
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+
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+#elif defined(CONFIG_ARCH_SUN8IW7P1)
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+#define SUNXI_SRAM_A1_PBASE (0x00000000)
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+#define SUNXI_SRAM_A1_SIZE (0x10000)
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+#define SUNXI_SRAM_A2_PBASE (0x40000)
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+#define SUNXI_SRAM_A2_SIZE (0xc000)
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+
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+#elif defined(CONFIG_ARCH_SUN8IW6P1)
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+#define SUNXI_SRAM_A1_PBASE (0x00000000)
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+#define SUNXI_SRAM_A1_SIZE (0x4000)
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+#define SUNXI_SRAM_A2_PBASE (0x44000)
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+#define SUNXI_SRAM_A2_SIZE (0x14000)
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+#define SUNXI_SRAM_C_SIZE (0x9000)
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+
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+#elif defined(CONFIG_ARCH_SUN50IW1P1)
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+#define SUNXI_SRAM_BROM_PBASE (0x00000000)
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+#define SUNXI_SRAM_BROM_SIZE (0x00010000)
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+#define SUNXI_SRAM_A1_PBASE (0x00010000)
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+#define SUNXI_SRAM_A1_SIZE (0x00008000)
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+#define SUNXI_SRAM_A2_PBASE (0x00040000)
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+#define SUNXI_SRAM_A2_SIZE (0x00014000)
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+#define SUNXI_SRAM_C_PBASE (0x00018000)
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+#define SUNXI_SRAM_C_SIZE (0x00028000)
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+#elif defined(CONFIG_ARCH_SUN8IW12P1) || defined(CONFIG_ARCH_SUN8IW15P1) \
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+ || defined(CONFIG_ARCH_SUN8IW18P1)
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+#define ARISC_MESSAGE_POOL_PBASE (0x48105000)
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+#define ARISC_MESSAGE_POOL_RANGE (0x1000)
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+#endif
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+
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+#endif /* __MACH_SUNXI_H */
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