mirror of https://github.com/OpenIPC/firmware.git
111 lines
4.0 KiB
Diff
111 lines
4.0 KiB
Diff
diff -drupN a/arch/arm/mach-sunxi/sun8iw17-setup.S b/arch/arm/mach-sunxi/sun8iw17-setup.S
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--- a/arch/arm/mach-sunxi/sun8iw17-setup.S 1970-01-01 03:00:00.000000000 +0300
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+++ b/arch/arm/mach-sunxi/sun8iw17-setup.S 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,106 @@
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+/*
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+ * linux/arch/arm/mach-sunxi/sun8i-setup.S
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+ *
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+ * Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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+ * http://www.allwinnertech.com
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+ *
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+ * Author: sunny <sunny@allwinnertech.com>
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+ *
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+ * allwinner sun8i cpu core power-up setup operations.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+
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+#include <linux/linkage.h>
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+#include <asm/mcpm.h>
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+
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+#define SLAVE_SNOOPCTL_OFFSET 0
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+#define SNOOPCTL_SNOOP_ENABLE (1 << 0)
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+#define SNOOPCTL_DVM_ENABLE (1 << 1)
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+
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+#define CCI_STATUS_OFFSET 0xc
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+#define STATUS_CHANGE_PENDING (1 << 0)
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+
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+#define CCI_SLAVE_OFFSET(n) (0x1000 + 0x1000 * (n))
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+
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+#define SUN8I_CCI_PHYS_BASE 0x030D0000
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+#define SUN8I_CCI_SLAVE_C0 3
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+#define SUN8I_CCI_SLAVE_C1 4
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+
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+#define SUN8I_CCI_C0_OFFSET CCI_SLAVE_OFFSET(SUN8I_CCI_SLAVE_C0)
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+#define SUN8I_CCI_C1_OFFSET CCI_SLAVE_OFFSET(SUN8I_CCI_SLAVE_C1)
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+
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+#define SUN8IW17_CCU_PHYS_BASE (0x03001000)
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+#define SUN8IW17_CCU_C0_AXI_CFG_OFFSET (0x500)
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+#define SUN8IW17_CCU_C1_AXI_CFG_OFFSET (0x504)
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+
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+ENTRY(sun8i_power_up_setup)
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+ mov r2, r0 @ backup r0 register first
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+ mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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+ ubfx r0, r0, #8, #4 @ cluster
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+ cmp r2, #0 @ if the cluster first-man
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+ beq 2f
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+
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+ @Config cluster0/cluster1 axi div to 3 and 4
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+ @If you don't kown why, please don't change the code.
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+ @by zhuzhenhua at 2014-7-10.
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+ cmp r0, #0 @ Cluster 0?
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+ bne cluster1_axi_setup
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+
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+cluster0_axi_setup:
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+ ldr r3, =SUN8IW17_CCU_PHYS_BASE + SUN8IW17_CCU_C0_AXI_CFG_OFFSET
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+ ldr r1, [r3]
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+ bic r1, r1, #(0x3<<0) @ cluster0 axi div
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+ orr r1, r1, #(0x3<<0) @ div = value + 1
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+ str r1, [r3] @ set axi div to 4
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+ dsb @ Synchronise side-effects of axi config
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+ @ make axi change from 4 to 3 force hardware update
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+ ldr r1, [r3]
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+ bic r1, r1, #(0x3<<0) @ cluster0 axi div
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+ orr r1, r1, #(0x2<<0) @ div = value + 1
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+ str r1, [r3] @ set axi div to 3
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+ dsb @ Synchronise side-effects of axi config
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+ b axi_setup_finish
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+
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+cluster1_axi_setup:
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+ ldr r3, =SUN8IW17_CCU_PHYS_BASE + SUN8IW17_CCU_C1_AXI_CFG_OFFSET
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+ ldr r1, [r3]
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+ bic r1, r1, #(0x3<<0) @ cluster1 axi div
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+ orr r1, r1, #(0x3<<0) @ div = value + 1
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+ str r1, [r3] @ set axi div to 4
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+ dsb @ Synchronise side-effects of axi config
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+ @ make axi change from 4 to 3 force hardware update
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+ ldr r1, [r3]
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+ bic r1, r1, #(0x3<<0) @ cluster1 axi div
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+ orr r1, r1, #(0x2<<0) @ div = value + 1
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+ str r1, [r3] @ set axi div to 3
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+ dsb @ Synchronise side-effects of axi config
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+
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+axi_setup_finish:
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+ @ cluster1/cluster0 may not require explicit L2 invalidation on reset, dependent
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+ @ on hardware integration desicions.
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+ @ For now, this code assumes that L2 is already invalidated by hardware.
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+ ldr r3, =SUN8I_CCI_PHYS_BASE + SUN8I_CCI_C0_OFFSET
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+ cmp r0, #0 @ cluster0?
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+ addne r3, r3, #SUN8I_CCI_C1_OFFSET - SUN8I_CCI_C0_OFFSET
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+
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+ @ r3 now points to the correct CCI slave register block
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+ ldr r1, [r3, #SLAVE_SNOOPCTL_OFFSET]
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+ orr r1, r1, #SNOOPCTL_SNOOP_ENABLE
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+ orr r1, r1, #SNOOPCTL_DVM_ENABLE
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+ str r1, [r3, #SLAVE_SNOOPCTL_OFFSET] @ enable CCI snoops
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+
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+ @ Wait for snoop control change to complete:
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+ ldr r3, =SUN8I_CCI_PHYS_BASE
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+1:
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+ ldr r1, [r3, #CCI_STATUS_OFFSET]
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+ tst r1, #STATUS_CHANGE_PENDING
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+ bne 1b
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+ dsb @ Synchronise side-effects of enabling CCI
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+2:
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+ bx lr
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+ENDPROC(sun8i_power_up_setup)
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