mirror of https://github.com/OpenIPC/firmware.git
90 lines
2.6 KiB
Diff
90 lines
2.6 KiB
Diff
diff -drupN a/arch/arm/mach-sunxi/sun8i-setup.S b/arch/arm/mach-sunxi/sun8i-setup.S
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--- a/arch/arm/mach-sunxi/sun8i-setup.S 1970-01-01 03:00:00.000000000 +0300
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+++ b/arch/arm/mach-sunxi/sun8i-setup.S 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,85 @@
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+/*
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+ * linux/arch/arm/mach-sunxi/sun8i-setup.S
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+ *
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+ * Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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+ * http://www.allwinnertech.com
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+ *
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+ * Author: sunny <sunny@allwinnertech.com>
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+ *
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+ * allwinner sun8i cpu core power-up setup operations.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+
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+#include <linux/linkage.h>
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+#include <asm/mcpm.h>
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+
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+
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+#define SLAVE_SNOOPCTL_OFFSET 0
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+#define SNOOPCTL_SNOOP_ENABLE (1 << 0)
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+#define SNOOPCTL_DVM_ENABLE (1 << 1)
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+
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+#define CCI_STATUS_OFFSET 0xc
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+#define STATUS_CHANGE_PENDING (1 << 0)
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+
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+#define CCI_SLAVE_OFFSET(n) (0x1000 + 0x1000 * (n))
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+
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+#define SUN8I_CCI_PHYS_BASE 0x01790000
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+#define SUN8I_CCI_SLAVE_A15 3
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+#define SUN8I_CCI_SLAVE_A7 4
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+
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+#define SUN8I_CCI_A15_OFFSET CCI_SLAVE_OFFSET(SUN8I_CCI_SLAVE_A15)
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+#define SUN8I_CCI_A7_OFFSET CCI_SLAVE_OFFSET(SUN8I_CCI_SLAVE_A7)
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+
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+
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+ENTRY(sun8i_power_up_setup)
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+
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+ cmp r0, #0 @ check affinity level
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+ beq 2f
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+
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+/*
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+ * Enable cluster-level coherency, in preparation for turning on the MMU.
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+ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
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+ * already restores that.
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+ */
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+
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+ mrc p15, 0, r0, c0, c0, 5 @ MPIDR
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+ ubfx r0, r0, #8, #4 @ cluster
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+
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+ @ A15/A7 may not require explicit L2 invalidation on reset, dependent
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+ @ on hardware integration desicions.
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+ @ For now, this code assumes that L2 is either already invalidated, or
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+ @ invalidation is not required.
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+
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+ ldr r3, =SUN8I_CCI_PHYS_BASE + SUN8I_CCI_A15_OFFSET
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+ cmp r0, #0 @ A15 cluster?
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+ addne r3, r3, #SUN8I_CCI_A7_OFFSET - SUN8I_CCI_A15_OFFSET
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+
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+ @ r3 now points to the correct CCI slave register block
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+
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+ ldr r0, [r3, #SLAVE_SNOOPCTL_OFFSET]
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+ orr r0, r0, #SNOOPCTL_SNOOP_ENABLE | SNOOPCTL_DVM_ENABLE
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+ str r0, [r3, #SLAVE_SNOOPCTL_OFFSET] @ enable CCI snoops
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+
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+ @ Wait for snoop control change to complete:
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+
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+ ldr r3, =SUN8I_CCI_PHYS_BASE
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+
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+1: ldr r0, [r3, #CCI_STATUS_OFFSET]
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+ tst r0, #STATUS_CHANGE_PENDING
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+ bne 1b
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+
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+ dsb @ Synchronise side-effects of enabling CCI
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+
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+ bx lr
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+
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+2: @ Implementation-specific local CPU setup operations should go here,
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+ @ if any. In this case, there is nothing to do.
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+
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+ bx lr
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+
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+ENDPROC(sun8i_power_up_setup)
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