mirror of https://github.com/OpenIPC/firmware.git
105 lines
3.2 KiB
Diff
105 lines
3.2 KiB
Diff
diff -drupN a/arch/arm/mach-sunxi/platsmp-v3.h b/arch/arm/mach-sunxi/platsmp-v3.h
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--- a/arch/arm/mach-sunxi/platsmp-v3.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/arch/arm/mach-sunxi/platsmp-v3.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,100 @@
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+/*
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+ * arch/arm/mach-sunxi/platsmp-v3.h
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+ *
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+ * Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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+ * http://www.allwinnertech.com
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+ *
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+ * Author: zhuxianbin <zhuxianbin@allwinnertech.com>
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+ *
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+ * sunxi smp ops header file for platform v1
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#ifndef __PLATSMP_V3_H__
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+#define __PLATSMP_V3_H__
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+
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+
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+#define SUNXI_R_PRCM_PBASE (0x01f01400)
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+#define SUNXI_R_CPUCFG_PBASE (0x01f01c00)
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+#define SUNXI_R_CPUCFG_VBASE IO_ADDRESS(SUNXI_R_CPUCFG_PBASE)
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+#define SUNXI_R_PRCM_VBASE IO_ADDRESS(SUNXI_R_PRCM_PBASE)
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+
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+static inline int sunxi_is_wfi_mode(int cpu)
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+{
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+ u32 r_cpucfg_vbase = (u32)SUNXI_R_CPUCFG_VBASE;
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+
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+ return (readl((void *)(r_cpucfg_vbase +
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+ CPUCFG_CPU_STATUS_REG(cpu))) & (1<<2));
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+}
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+
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+static inline void sunxi_enable_cpu(int cpu)
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+{
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+ u32 pwr_reg;
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+ u32 r_prcm_v;
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+ u32 r_cpucfg_v;
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+
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+ r_prcm_v = (u32)SUNXI_R_PRCM_VBASE;
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+ r_cpucfg_v = (u32)SUNXI_R_CPUCFG_VBASE;
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+ /* step1: Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW.
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+ * Ensure DBGPWRDUP is held LOW to prevent any external
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+ * debug access to the processor.
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+ */
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+ /* assert cpu core reset */
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+ writel(0, (void *)(r_cpucfg_v + CPUCFG_CPU_RST_CTRL_REG(cpu)));
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+ /* L1RSTDISABLE hold low */
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+ pwr_reg = readl((void *)(r_cpucfg_v + CPUCFG_GEN_CTRL_REG));
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+ pwr_reg &= ~(1<<cpu);
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+ writel(pwr_reg, (void *)(r_cpucfg_v + CPUCFG_GEN_CTRL_REG));
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+ udelay(10);
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+
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+ /* step2: release power clamp */
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+ writel(0xFE, (void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu)));
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+ udelay(20);
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+ writel(0xF8, (void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu)));
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+ udelay(10);
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+ writel(0xE0, (void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu)));
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+ udelay(10);
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+ writel(0x80, (void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu)));
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+ udelay(10);
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+ writel(0x00, (void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu)));
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+ udelay(20);
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+
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+ while (readl((void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu))))
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+ ;
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+
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+
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+ /* step3: clear power-off gating */
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+ pwr_reg = readl((void *)(r_prcm_v + PRCM_CPU_PWROFF_REG));
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+ pwr_reg &= ~(0x00000001<<cpu);
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+ writel(pwr_reg, (void *)(r_prcm_v + PRCM_CPU_PWROFF_REG));
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+ udelay(20);
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+
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+ /* step4: de-assert core reset */
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+ writel(3, (void *)(r_cpucfg_v + CPUCFG_CPU_RST_CTRL_REG(cpu)));
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+}
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+
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+static inline void sunxi_disable_cpu(int cpu)
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+{
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+ u32 pwr_reg;
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+ u32 r_prcm_v = (u32)SUNXI_R_PRCM_VBASE;
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+
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+ /* step1: set up power-off signal */
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+ pwr_reg = readl((void *)(r_prcm_v + PRCM_CPU_PWROFF_REG));
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+ pwr_reg |= (1<<cpu);
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+ writel(pwr_reg, (void *)(r_prcm_v + PRCM_CPU_PWROFF_REG));
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+ udelay(20);
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+
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+ /* step2: active the power output clamp */
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+ writel(0xff, (void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu)));
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+ udelay(30);
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+ while (readl((void *)(r_prcm_v + PRCM_CPU_PWR_CLAMP_REG(cpu))) != 0xff)
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+ ;
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+
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+}
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+
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+#endif /*__PLATSMP_V3_H__*/
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+
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