mirror of https://github.com/OpenIPC/firmware.git
124 lines
3.5 KiB
Diff
124 lines
3.5 KiB
Diff
diff -drupN a/arch/arm/mach-sunxi/platsmp-v1.h b/arch/arm/mach-sunxi/platsmp-v1.h
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--- a/arch/arm/mach-sunxi/platsmp-v1.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/arch/arm/mach-sunxi/platsmp-v1.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,119 @@
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+/*
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+ * arch/arm/mach-sunxi/platsmp-v1.h
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+ *
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+ * Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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+ * http://www.allwinnertech.com
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+ *
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+ * Author: east_yang <yangdong@allwinnertech.com>
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+ *
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+ * sunxi smp ops header file for platform v1
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#ifndef __PLATSMP_V1_H__
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+#define __PLATSMP_V1_H__
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+
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+static inline int sunxi_is_wfi_mode(int cpu)
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+{
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+#ifdef CONFIG_EVB_PLATFORM
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+ return readl(sunxi_cpucfg_base + CPUCFG_CPU_STATUS_REG(cpu)) & (1<<2);
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+#else
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+ return 1;
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+#endif
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+}
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+
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+static inline void sunxi_enable_cpu(int cpu)
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+{
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+ unsigned int value;
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+
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+ /* Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW.
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+ * Ensure DBGPWRDUP is held LOW to prevent any external
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+ * debug access to the processor.
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+ */
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+ /* assert cpu core reset */
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+ writel(0, sunxi_cpucfg_base + CPUCFG_CPU_RST_CTRL_REG(cpu));
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+
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+ /* L1RSTDISABLE hold low */
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+ value = readl(sunxi_cpucfg_base + CPUCFG_GEN_CTRL_REG);
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+
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+ value &= ~(1<<cpu);
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+ writel(value, sunxi_cpucfg_base + CPUCFG_GEN_CTRL_REG);
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+ udelay(10);
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+
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+ /* DBGPWRDUP hold low */
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+ value = readl(sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
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+
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+ value &= ~(1<<cpu);
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+ writel(value, sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
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+
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+#ifndef CONFIG_ARCH_SUN8IW10
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+ /* Release power switch */
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+ writel(0xFE, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
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+ udelay(20);
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+ writel(0xF8, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
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+ udelay(10);
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+ writel(0xE0, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
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+ udelay(10);
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+ writel(0x80, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
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+ udelay(10);
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+ writel(0x00, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
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+ udelay(20);
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+ while (readl(sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu)) != 0x00)
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+ ;
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+
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+ /* Clear power-off gating */
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+ value = readl((void *)(sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG));
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+ value &= ~(1<<cpu);
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+ writel(value, (void *)(sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG));
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+ udelay(20);
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+#endif
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+
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+ /* de-assert core reset */
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+ writel(3, sunxi_cpucfg_base + CPUCFG_CPU_RST_CTRL_REG(cpu));
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+
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+ /* assert DBGPWRDUP signal */
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+ value = readl(sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
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+ value |= (1<<cpu);
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+ writel(value, sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
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+}
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+
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+#ifdef CONFIG_ARCH_SUN8IW10
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+/*
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+ * The cpu of SUN8IW10 can not be powered off independently.
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+ */
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+static inline void sunxi_disable_cpu(int cpu)
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+{
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+ /* do nothing */
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+}
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+#else
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+static inline void sunxi_disable_cpu(int cpu)
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+{
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+ unsigned int value;
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+
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+ /* assert cpu core reset */
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+ writel(0, sunxi_cpucfg_base + CPUCFG_CPU_RST_CTRL_REG(cpu));
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+
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+ /* DBGPWRDUP hold low */
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+ value = readl(sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
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+ value &= ~(1<<cpu);
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+ writel(value, sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
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+
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+ /* power gating off */
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+ value = readl(sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG);
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+ value |= (1<<cpu);
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+ writel(value, sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG);
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+ udelay(20);
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+
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+ /* power switch off */
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+ writel(0xff, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
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+ udelay(30);
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+ while (readl(sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu)) != 0xff)
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+ ;
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+}
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+#endif
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+
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+#endif /* __PLATSMP_V1_H__ */
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