mirror of https://github.com/OpenIPC/firmware.git
289 lines
7.4 KiB
Diff
289 lines
7.4 KiB
Diff
diff -drupN a/sound/soc/sunxi/sun8iw17-codec.h b/sound/soc/sunxi/sun8iw17-codec.h
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--- a/sound/soc/sunxi/sun8iw17-codec.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/sound/soc/sunxi/sun8iw17-codec.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,284 @@
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+/*
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+ * sound\soc\sunxi\sun8iw11codec.h
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+ * (C) Copyright 2014-2016
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+ * allwinner Technology Co., Ltd. <www.allwinnertech.com>
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+ * huangxin <huangxin@allwinnertech.com>
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+ *
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+ * some simple description for this code
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ */
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+#ifndef _SUN8IW17_CODEC_H
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+#define _SUN8IW17_CODEC_H
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+
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+#define SUNXI_CODEC_CPUDAI_RX_CHANNELS_MAX 3
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+#define SUNXI_CODEC_CPUDAI_TX_CHANNELS_MAX 2
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+
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+#define SUNXI_DAC_DPC 0x00
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+#define SUNXI_DAC_FIFO_CTR 0x10
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+#define SUNXI_DAC_FIFO_STA 0x14
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+/* left blank */
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+#define SUNXI_DAC_TXDATA 0X20
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+#define SUNXI_DAC_CNT 0x24
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+#define SUNXI_DAC_DG 0x28
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+#define SUNXI_ADC_FIFO_CTR 0x30
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+#define SUNXI_ADC_FIFO_STA 0x38
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+#define SUNXI_ADC_RXDATA 0x40
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+/* left blank */
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+#define SUNXI_ADC_CNT 0x44
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+#define SUNXI_ADC_DG 0x4C
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+
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+/*left blank */
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+#define SUNXI_DAC_DAP_CTR 0xf0
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+#define SUNXI_ADC_DAP_CTR 0xf8
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+#define SUNXI_ADC_DRC_HHPFC 0x200
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+#define SUNXI_ADC_DRC_LHPFC 0x204
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+
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+/* Analog register base - Digital register base */
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+/*SUNXI_PR_CFG is to tear the acreg and dcreg, it is of no real meaning*/
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+#define SUNXI_PR_CFG 0x300
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+#define SUNXI_LOMIX_SRC (SUNXI_PR_CFG + 0x01)
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+#define SUNXI_ROMIX_SRC (SUNXI_PR_CFG + 0x02)
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+#define SUNXI_DAC_PA_SRC (SUNXI_PR_CFG + 0x03)
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+#define SUNXI_LINEIN_GCTR (SUNXI_PR_CFG + 0x04)
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+#define SUNXI_LINEINLR_MIC1_GCTR (SUNXI_PR_CFG + 0x05)
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+#define SUNXI_MIC2_MIC3_GCTR (SUNXI_PR_CFG + 0x06)
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+#define SUNXI_PHONEOUT_CTR (SUNXI_PR_CFG + 0x07)
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+#define SUNXI_PHOMIX_MICBIAS_CTR (SUNXI_PR_CFG + 0x08)
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+#define SUNXI_LINEOUT_VOL (SUNXI_PR_CFG + 0x09)
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+#define SUNXI_MIC1B_LINEOUT_CTR (SUNXI_PR_CFG + 0x0A)
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+#define SUNXI_MIC2B_MIC3B (SUNXI_PR_CFG + 0x0B)
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+/* left blank */
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+#define SUNXI_LADCMIX_SRC (SUNXI_PR_CFG + 0x0C)
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+#define SUNXI_RADCMIX_SRC (SUNXI_PR_CFG + 0x0D)
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+#define SUNXI_XADCMIX_SRC (SUNXI_PR_CFG + 0x0E)
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+#define SUNXI_ADC_AP_EN (SUNXI_PR_CFG + 0x0F)
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+#define SUNXI_OP_CTR0 (SUNXI_PR_CFG + 0x10)
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+#define SUNXI_OP_CTR1 (SUNXI_PR_CFG + 0x11)
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+#define SUNXI_USB_BIAS_CTR (SUNXI_PR_CFG + 0x12)
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+#define SUNXI_ADC_FUN_CTR (SUNXI_PR_CFG + 0x13)
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+#define SUNXI_BIAS_DA16_CAL_CTR (SUNXI_PR_CFG + 0x14)
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+#define SUNXI_DA16_CALI_DATA (SUNXI_PR_CFG + 0x15)
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+/* left blank */
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+#define SUNXI_BIAS_CALI_DATA (SUNXI_PR_CFG + 0x17)
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+#define SUNXI_BIAS_CALI_SET (SUNXI_PR_CFG + 0x18)
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+
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+/* SUNXI_DAC_DPC:0x00 */
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+#define EN_DAC 31
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+#define MODQU 25
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+#define DWA_EN 24
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+#define HPF_EN 18
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+#define DVOL 12
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+#define DAC_HUB_EN 0
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+
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+/* SUNXI_DAC_FIFO_CTR:0x10 */
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+#define DAC_FS 29
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+#define FIR_VER 28
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+#define SEND_LASAT 26
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+#define FIFO_MODE 24
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+#define DAC_DRQ_CLR_CNT 21
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+#define TX_TRIG_LEVEL 8
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+#define DAC_MONO_EN 6
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+#define TX_SAMPLE_BITS 5
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+#define DAC_DRQ_EN 4
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+#define DAC_IRQ_EN 3
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+#define FIFO_UNDERRUN_IRQ_EN 2
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+#define FIFO_OVERRUN_IRQ_EN 1
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+#define FIFO_FLUSH 0
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+/* SUNXI_DAC_FIFO_STA:0x14 */
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+#define TX_EMPTY 23
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+#define DAC_TXE_CNT 8
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+#define DAC_TXE_INT 3
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+#define DAC_TXU_INT 2
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+#define DAC_TXO_INT 1
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+/* SUNXI_ADC_FIFO_CTR:0x30 */
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+#define ADC_FS 29
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+#define EN_AD 28
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+#define ADCFDT 26
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+#define ADCDFEN 25
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+#define RX_FIFO_MODE 24
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+#define RX_SAMPLE_BITS 16
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+#define ADC_CHAN_SEL 12
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+#define RX_FIFO_TRG_LEVEL 4
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+#define ADC_DRQ_EN 3
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+#define ADC_IRQ_EN 2
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+#define ADC_OVERRUN_IRQ_EN 1
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+#define ADC_FIFO_FLUSH 0
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+/* SUNXI_ADC_FIFO_STA:0x38 */
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+#define RXA 23
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+#define ADC_RXA_CNT 8
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+#define ADC_RXA_INT 3
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+#define ADC_RXO_INT 1
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+/* SUNXI_DAC_DAP_CTR:0xf0 */
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+#define DDAP_EN 31
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+#define DDAP_DRC_EN 29
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+#define DDAP_HPF_EN 28
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+/* SUNXI_ADC_DAP_CTR:0xf8 */
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+#define ADC_DAP0_EN 31
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+#define ADC_DRC0_EN 29
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+#define ADC_HPF0_EN 28
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+#define ADC_DAP1_EN 27
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+#define ADC_DRC1_EN 25
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+#define ADC_HPF1_EN 24
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+/*SUNXI_ADC_DRC_HHPFC : 0x200*/
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+#define ADC_HHPF_CONF 0
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+/*SUNXI_ADC_DRC_LHPFC : 0x204*/
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+#define ADC_LHPF_CONF 0
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+
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+/* SUNXI_PR_CFG:0x07010280 */
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+#define AC_PR_RST 28
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+#define AC_PR_RW 24
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+#define AC_PR_ADDR 16
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+#define ADDA_PR_WDAT 8
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+#define ADDA_PR_RDAT 0
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+
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+
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+/* SUNXI_LOMIX_SRC:0x01 */
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+#define LMIXMUTE 0
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+#define LMIX_MIC1_BST 6
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+#define LMIX_MIC2_BST 5
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+#define LMIX_MIC3_BST 4
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+#define LMIX_LINEINLR 3
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+#define LMIX_LINEINL 2
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+#define LMIX_LDAC 1
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+#define LMIX_RDAC 0
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+
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+/* SUNXI_ROMIX_SRC:0x02 */
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+#define RMIXMUTE 0
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+#define RMIX_MIC1_BST 6
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+#define RMIX_MIC2_BST 5
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+#define RMIX_MIC3_BST 4
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+#define RMIX_LINEINLR 3
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+#define RMIX_LINEINR 2
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+#define RMIX_RDAC 1
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+#define RMIX_LDAC 0
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+
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+
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+/* SUNXI_DAC_PA_SRC:0x03 */
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+#define DACAREN 7
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+#define DACALEN 6
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+#define RMIXEN 5
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+#define LMIXEN 4
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+
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+
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+/* SUNXI_LINEIN_GCTR:0x04 */
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+#define LINEINLG 4
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+#define LINEINRG 0
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+
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+/* SUNXI_LINEINLR_MIC1_GCTR:0x05 */
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+#define LINEING 4
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+#define MIC1_GAIN 0
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+
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+
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+/* SUNXI_MIC2_MIC3_GCTR:0x06 */
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+#define MIC2_GAIN 4
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+#define MIC3_GAIN 0
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+
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+/* SUNXI_PHONEOUT_CTR:0x07 */
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+#define PHONEOUTEN 3
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+#define PHONEOUTG 0
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+
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+/* SUNXI_PHOMIX_MICBIAS_CTR:0x08 */
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+#define MMICBIASEN 6
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+
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+#define PHOMIXMUTE 0
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+#define PH0MIX_LINEINLR 5
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+#define PHOMIX_MIC3_BST 4
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+#define PHOMIX_MIC1_BST 3
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+#define PHOMIX_MIC2_BST 2
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+#define PHOMIX_ROUT_MIX 1
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+#define PHOMIX_LOUT_MIX 0
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+
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+/* SUNXI_LINEOUT_VOL:0x09 */
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+#define LINEOUT_VOL 3
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+#define LINEIN_BOOST 0
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+
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+/* SUNXI_MIC1B_LINEOUT_CTR:0x0A*/
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+#define LINEOUTL_EN 7
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+#define LINEOUTR_EN 6
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+#define LINEOUTL_SRC 5
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+#define LINEOUTR_SRC 4
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+#define MIC1AMPEN 3
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+#define MIC1BOOST 0
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+
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+/* SUNXI_MIC2B_MIC3B:0x0B*/
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+#define MIC2AMPEN 7
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+#define MIC2BOOST 4
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+#define MIC3AMPEN 3
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+#define MIC3BOOST 0
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+
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+/* SUNXI_LADCMIX_SRC:0x0C */
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+#define LADCMIXMUTE 0
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+#define LADC_MIC1_BST 6
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+#define LADC_MIC2_BST 5
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+#define LADC_MIC3_BST 4
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+#define LADC_LINEINLR 3
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+#define LADC_LINEINL 2
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+#define LADC_LOUT_MIX 1
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+#define LADC_ROUT_MIX 0
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+
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+/* SUNXI_RADCMIX_SRC:0x0D */
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+#define RADCMIXMUTE 0
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+#define RADC_MIC1_BST 6
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+#define RADC_MIC2_BST 5
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+#define RADC_MIC3_BST 4
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+#define RADC_LINEINLR 3
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+#define RADC_LINEINR 2
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+#define RADC_ROUT_MIX 1
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+#define RADC_LOUT_MIX 0
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+
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+/* SUNXI_XADCMIX_SRC:0x0E */
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+#define XADCMIXMUTE 0
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+#define XADC_MIC1_BST 6
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+#define XADC_MIC2_BST 5
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+#define XADC_MIC3_BST 4
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+#define XADC_LINEINLR 3
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+#define XADC_ROUT_MIX 1
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+#define XADC_LOUT_MIX 0
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+
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+/* SUNXI_ADC_AP_EN:0x0F */
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+#define ADCREN 7
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+#define ADCLEN 6
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+#define ADCXEN 5
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+#define ADCG 0
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+
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+/* SUNXI_OP_CTR0:0x10 */
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+#define OPADC1_BIAS_CUR 4
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+#define OPADC2_BIAS_CUR 2
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+#define OPAAF_BIAS_CUR 0
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+
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+/* SUNXI_OP_CTR1:0x11 */
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+#define OPMIC_BIAS_CUR 6
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+#define OPVR_BIAS_CUR 4
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+#define OPDAC_BIAS_CUR 2
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+#define OPMIX_BIAS_CUR 0
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+
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+/* SUNXI_USB_BIAS_CTR:0x12 */
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+#define USB_BIAS_CUR 0
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+
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+/* SUNXI_ADC_FUN_CTR:0x13 */
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+#define MMIC_BIAS_CHOP_EN 7
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+#define MMIC_BIAS_CHOP_SRC 5
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+#define DITHER 4
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+#define DITHER_CLK_SEL 2
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+#define BIHE_CTRL 0
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+
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+/* SUNXI_BIAS_DA16_CAL_CTR:0x14*/
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+#define PA_SPEED_SELECT 7
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+#define CUR_TEST_SEL 6
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+#define BIAS_DA16_CLK_SEL 4
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+#define BIAS_CAL_MODE_SEL 3
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+#define BIAS_DA16_CAL_CTRL 2
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+#define BIAS_CAL_VER 1
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+
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+/* SUNXI_BIAS_CALI_DATA:0x17*/
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+#define BIAS_CALI 0
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+
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+/* SUNXI_BIAS_CALI_SET:0x18*/
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+#define BIAS_VERIFY 0
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+
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+#endif /* __SUN8IW17_CODEC_H */
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